The first three patches are ones that I have pulled out of my original Hypervisor series at an attempt to reduce the number of patches in the series.
These three patches all make sense without the Hypervisor series so can be merged seperatley and will reduce the review burden of the next version of the patches. The fource patch is a prep patch for the new v0.4 Hypervisor spec. The fifth patch is unreleated to Hypervisor that I'm just slipping in here because it seems easier then sending it by itself. The final two patches are issues I discovered while adding the v0.4 Hypervisor extension. v3: - Change names of all GP registers - Add two more patches v2: - Small corrections based on feedback - Remove the CSR permission check patch Alistair Francis (6): target/riscv: Don't set write permissions on dirty PTEs riscv: plic: Remove unused interrupt functions target/riscv: Create function to test if FP is enabled target/riscv: Update the Hypervisor CSRs to v0.4 target/riscv: Fix mstatus dirty mask target/riscv: Convert mip to target_ulong Atish Patra (1): target/riscv: Use both register name and ABI name hw/riscv/sifive_plic.c | 12 ------------ include/hw/riscv/sifive_plic.h | 3 --- target/riscv/cpu.c | 19 ++++++++++-------- target/riscv/cpu.h | 8 ++++++-- target/riscv/cpu_bits.h | 35 +++++++++++++++++----------------- target/riscv/cpu_helper.c | 16 ++++++++++++---- target/riscv/csr.c | 22 +++++++++++---------- 7 files changed, 59 insertions(+), 56 deletions(-) -- 2.22.0