On Mon, 19 Aug 2019 at 22:38, Richard Henderson <richard.hender...@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > target/arm/translate.c | 150 ++++++++++++++--------------------- > target/arm/a32-uncond.decode | 8 ++ > target/arm/t32.decode | 12 +++ > 3 files changed, 81 insertions(+), 89 deletions(-) > > diff --git a/target/arm/translate.c b/target/arm/translate.c > index b6d8b7be8c..e268c5168d 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -9980,16 +9980,71 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) > return true; > } > > +/* > + * Unconditional system instructions > + */ > + > +static bool trans_RFE(DisasContext *s, arg_RFE *a) > +{ > + int32_t offset; > + TCGv_i32 addr, t1, t2; > + > + if (IS_USER(s) || !ENABLE_ARCH_6) { > + return false; > + }
The legacy thumb decoder for RFE and SRS also has "not if M profile", which we seem to be missing here ? > diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode > index 573ac2cf8e..3b961233e5 100644 > --- a/target/arm/a32-uncond.decode > +++ b/target/arm/a32-uncond.decode > @@ -29,3 +29,11 @@ > %imm24h 0:s24 24:1 !function=times_2 > > BLX_i 1111 101 . ........................ &i imm=%imm24h > + > +# System Instructions > + > +&rfe rn w pu > +&srs mode w pu > + > +RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe > +SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs Is this SRS encoding correct? The copy of the Arm ARM I'm looking at thinks that it starts 1111 100, the same as RFE. Otherwise Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM