Yes, we don't currently implement most of the 'trap system register access' bits in HCR_EL2. Last time I checked we were missing TID0 TID1 TID2 TID3 TIDCP TAC TSW TPC TPU TTLB TVM TRVM TDZ, but it's possible we've implemented one or two of those since then.
** Changed in: qemu Status: New => Confirmed ** Summary changed: - HCR.TID3 traps are not implemented + arm emulation of HCR.TID3 traps are not implemented -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1843254 Title: arm emulation of HCR.TID3 traps are not implemented Status in QEMU: Confirmed Bug description: On ARM (aarch64), HCR_EL2.TID3 [bit18] is supposed to trap ID group 3, which includes the ID_AA64{PFR,DFR,ISAR,MMFR,AFR}*_EL1 registers. However, setting that HCR bit has no effect and accesses to those ID registers are not trapped to EL2 with an EC syndrome value of 0x18. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1843254/+subscriptions