Features: * support specification riscv-v-spec-0.7.1(https://content.riscv.org/wp-content/uploads/2019/06/17.40-Vector_RISCV-20190611-Vectors.pdf). * support basic vector extension. * support Zvlsseg. * support Zvamo. * not support Zvediv as it is changing. * fixed VLEN 128bit. * fixed SLEN 128bit. * ELEN support 8bit, 16bit, 32bit, 64bit.
Todo: * support VLEN configure from qemu command line. * move check code from execution-time to translation-time Changelog: V2 * use float16_compare{_quiet} * only use GETPC() in outer most helper * add ctx.ext_v Property LIU Zhiwei (17): RISC-V: add vfp field in CPURISCVState RISC-V: turn on vector extension from command line by cfg.ext_v Property RISC-V: support vector extension csr RISC-V: add vector extension configure instruction RISC-V: add vector extension load and store instructions RISC-V: add vector extension fault-only-first implementation RISC-V: add vector extension atomic instructions RISC-V: add vector extension integer instructions part1, add/sub/adc/sbc RISC-V: add vector extension integer instructions part2, bit/shift RISC-V: add vector extension integer instructions part3, cmp/min/max RISC-V: add vector extension integer instructions part4, mul/div/merge RISC-V: add vector extension fixed point instructions RISC-V: add vector extension float instruction part1, add/sub/mul/div RISC-V: add vector extension float instructions part2, sqrt/cmp/cvt/others RISC-V: add vector extension reduction instructions RISC-V: add vector extension mask instructions RISC-V: add vector extension premutation instructions linux-user/riscv/cpu_loop.c | 7 + target/riscv/Makefile.objs | 2 +- target/riscv/cpu.c | 6 +- target/riscv/cpu.h | 30 + target/riscv/cpu_bits.h | 15 + target/riscv/cpu_helper.c | 7 + target/riscv/csr.c | 65 +- target/riscv/helper.h | 358 + target/riscv/insn32.decode | 373 + target/riscv/insn_trans/trans_rvv.inc.c | 490 + target/riscv/translate.c | 1 + target/riscv/vector_helper.c | 25701 ++++++++++++++++++++++++++++++ 12 files changed, 27049 insertions(+), 6 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c create mode 100644 target/riscv/vector_helper.c -- 2.7.4