Hi Jim, On Tue, Oct 8, 2019 at 5:17 AM Jim Wilson <j...@sifive.com> wrote: > > On 10/4/19 8:16 AM, Jonathan Behrens wrote: > > diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml > > index 0d07aaec85..d6d76aafd8 100644 > > --- a/gdb-xml/riscv-32bit-cpu.xml > > +++ b/gdb-xml/riscv-32bit-cpu.xml > > @@ -44,4 +44,5 @@ > > <reg name="t5" bitsize="32" type="int"/> > > <reg name="t6" bitsize="32" type="int"/> > > <reg name="pc" bitsize="32" type="code_ptr"/> > > + <reg name="priv" bitsize="32" type="int"/> > > </feature> > > Adding this to the cpu register set means that the gdb "info registers" > command will now list a value for the mysterious undocumented "priv"
My gdb does not list "priv" register after applying this patch. >>> info registers ra 0x0 0x0 sp 0x0 0x0 gp 0x0 0x0 tp 0x0 0x0 t0 0x1000 4096 t1 0x0 0 t2 0x0 0 fp 0x0 0x0 s1 0x0 0 a0 0x0 0 a1 0x1020 4128 a2 0x0 0 a3 0x0 0 a4 0x0 0 a5 0x0 0 a6 0x0 0 a7 0x0 0 s2 0x0 0 s3 0x0 0 s4 0x0 0 s5 0x0 0 s6 0x0 0 s7 0x0 0 s8 0x0 0 s9 0x0 0 s10 0x0 0 s11 0x0 0 t3 0x0 0 t4 0x0 0 t5 0x0 0 t6 0x0 0 pc 0x1008 0x1008 Anything I was missing? > register. That is likely to result in user confusion, and a few gdb bug > reports. > > Gdb incidentally already has support for a virtual priv register. From > gdb/riscv-tdep.c: > > static const struct riscv_register_feature riscv_virtual_feature = > { > "org.gnu.gdb.riscv.virtual", > { > { RISCV_PRIV_REGNUM, { "priv" }, false } > } > }; > > So the correct way to fix this is to add a > gdb-xml/riscv-32bit-virtual.xml file, along with code to handle this new > xml file and the registers in it. Likewise for the 64-bit support. > > The main advantage of doing things this way is that only people that > care about the priv register will see it, and this will interoperate > with other RISC-V debuggers and targets (if any) that already have > virtual priv register support. Regards, Bin