On 08/01/2020 12:06, David Gibson wrote:
> On Tue, Jan 07, 2020 at 03:21:42PM +0100, Cédric Le Goater wrote:
>> On 1/7/20 5:48 AM, David Gibson wrote:
>>> The table of RMA limits based on the LPCR[RMLS] field is slightly wrong.
>>> We're missing the RMLS == 0 => 256 GiB RMA option, which is available on
>>> POWER8, so add that.
>>
>> Where is this defined ?
>
> It's in the Book4, so not easily available, unfortunately :(.
It is in "User’s Manual Single-Chip Module POWER8 Processor" which is
public.
>
>>> The comment that goes with the table is much more wrong. We *don't* filter
>>> invalid RMLS values when writing the LPCR, and there's not really a
>>> sensible way to do so. Furthermore, while in theory the set of RMLS values
>>> is implementation dependent, it seems in practice the same set has been
>>> available since around POWER4+ up until POWER8, the last model which
>>> supports RMLS at all. So, correct that as well.
>>>
>>> Signed-off-by: David Gibson <da...@gibson.dropbear.id.au>
>>> ---
>>> target/ppc/mmu-hash64.c | 8 ++++----
>>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
>>> index bb9ebeaf48..e6f24be93e 100644
>>> --- a/target/ppc/mmu-hash64.c
>>> +++ b/target/ppc/mmu-hash64.c
>>> @@ -760,12 +760,12 @@ static target_ulong rmls_limit(PowerPCCPU *cpu)
>>> {
>>> CPUPPCState *env = &cpu->env;
>>> /*
>>> - * This is the full 4 bits encoding of POWER8. Previous
>>> - * CPUs only support a subset of these but the filtering
>>> - * is done when writing LPCR
>>> + * In theory the meanings of RMLS values are implementation
>>> + * dependent. In practice, this seems to have been the set from
>>> + * POWER4+..POWER8, and RMLS is no longer supported in POWER9.
>>> */
>>> const target_ulong rma_sizes[] = {
>>> - [0] = 0,
>>> + [0] = 256 * GiB,
>>> [1] = 16 * GiB,
>>> [2] = 1 * GiB,
>>> [3] = 64 * MiB,
>>>
>>
>
--
Alexey
