> On 15 Jan 2020, at 23:28, Richard Henderson <richard.hender...@linaro.org>
> For risc-v, the odd nop-full semi-hosting call sequence
That unfortunate call sequence was the least worst compromise that the RISC-V
design team could agree on. :-(
The actual problem was that the RISC-V instruction set has a single BREAK op
code, without any way to parametrise it, and they refused to spend another op
code for an extra BREAK.
> was chosen to work with
> jtag debuggers on real silicon.
Yes, I know at least two, SEGGER J-Link of OpenOCD.
But again, there is nothing in the silicon related to the odd call sequence or
the ABI, everything is implemented in the debuggers. The silicon has only to
break to the debugger, then it's up to the debugger to decide if this is a
semihosting call or a regular break.
> ... they did have the opportunity to do better, and did not.
I don't know why you present Arm semihosting as a disaster. It is not perfect,
but it is functional, and common unit tests use only a small subset of the
And there is no 'window of opportunity', if the RISC-V guys will ever want to
reinvent the wheel and come with an official 'RISC-V semihosting' specs, they
can do it at any time, and this will have no impact on existing devices,
everything will continue to work as before, only the debuggers/emulators will
need to be upgraded.
But the only immediate effect such a move will have is that software efforts in
test frameworks will be increased, to support another protocol, while the
advantages will be minimal.