On 1/27/20 6:10 AM, Ian Jiang wrote: > The function that makes NaN-boxing when a 32-bit value is assigned > to a 64-bit FP register is split out to a helper gen_nanbox_fpr(). > Then it is applied in translating of the FLW instruction. > > This also applies for other instructions when the RVD extension is > present, such as FMV.W.W, FADD.S, FSUB.S and so on.
I wouldn't mention this yet, as it begs the question of what you are doing about it. Which is nothing, yet, since that will apply to a follow-up patch. > > Signed-off-by: Ian Jiang <ianjiang....@gmail.com> > --- > target/riscv/insn_trans/trans_rvf.inc.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
