On Mon, 3 Feb 2020 at 14:47, Richard Henderson <richard.hender...@linaro.org> wrote: > > For aarch64, there's a dedicated msr (imm, reg) insn. > For aarch32, this is done via msr to cpsr; and writes > from el0 are ignored. > > Since v8.0, the CPSR_RESERVED bits have been allocated. > We are not yet implementing ARMv8.0-SSBS or ARMv8.4-DIT, > so retain CPSR_RESERVED for now, so that the bits remain RES0.
...we removed CPSR_RESERVED in patch 8... > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > v2: Move regdef to file scope; merge patch for CPSR_RESERVED: > do not remove CPSR_SSBS from CPSR_RESERVED yet, mask PAN > from CPSR if feature not enabled (pmm). > v3: Update for cpsr_valid_mask etc. > --- > target/arm/cpu.h | 2 ++ > target/arm/internals.h | 6 ++++++ > target/arm/helper.c | 21 +++++++++++++++++++++ > target/arm/translate-a64.c | 14 ++++++++++++++ > 4 files changed, 43 insertions(+) Other than fixing up the commit message Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
