Arm GIC in Zynq SOC implements 5 priority bits i.e bits 7..3. Signed-off-by: Sai Pavan Boddu <sai.pavan.bo...@xilinx.com> --- hw/arm/xilinx_zynq.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3a0fa5b..7aa43ad 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -214,6 +214,7 @@ static void zynq_init(MachineState *machine) dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", 1); + qdev_prop_set_uint32(dev, "num-priority-bits", 5); qdev_init_nofail(dev); busdev = SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); -- 2.7.4