All remaining tests for VFP4 are for fused multiply-add insns. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> --- target/arm/cpu.h | 5 +++++ target/arm/translate-vfp.inc.c | 12 ++++++++---- target/arm/translate.c | 2 +- 3 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4ff28418df..f27b8e35df 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3468,6 +3468,11 @@ static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; } +static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) +{ + return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; +} + static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) { return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 8913320259..f6f7601fe2 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1806,8 +1806,10 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a) * In v7A, UNPREDICTABLE with non-zero vector length/stride; from * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || - (s->vec_len != 0 || s->vec_stride != 0)) { + if (!dc_isar_feature(aa32_simdfmac, s)) { + return false; + } + if (s->vec_len != 0 || s->vec_stride != 0) { return false; } @@ -1864,8 +1866,10 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a) * In v7A, UNPREDICTABLE with non-zero vector length/stride; from * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || - (s->vec_len != 0 || s->vec_stride != 0)) { + if (!dc_isar_feature(aa32_simdfmac, s)) { + return false; + } + if (s->vec_len != 0 || s->vec_stride != 0) { return false; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 3b9bf13933..0da780102c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4877,7 +4877,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } break; case NEON_3R_VFM_VQRDMLSH: - if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { + if (!dc_isar_feature(aa32_simdfmac, s)) { return 1; } break; -- 2.20.1