On Tue, 18 Feb 2020 at 19:10, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> This bit traps EL1 access to cache maintenance insns that operate
> to the point of coherency or persistence.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/helper.c | 39 +++++++++++++++++++++++++++++++--------
> 1 file changed, 31 insertions(+), 8 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 52b6e68659..ed34d4200f 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -4314,6 +4314,28 @@ static CPAccessResult aa64_cacheop_access(CPUARMState
> *env,
> return CP_ACCESS_OK;
> }
>
> +static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
> + const ARMCPRegInfo *ri,
> + bool isread)
> +{
> + /* Cache invalidate/clean to Point of Coherency or Persistence... */
> + switch (arm_current_el(env)) {
> + case 0:
> + /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
> + if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
> + return CP_ACCESS_TRAP;
> + }
> + break;
If we're at EL0 and SCTLR.UCI is set, then we should fall
through to honour the HCR_EL2.TPCP check, not always-succeed.
> + case 1:
> + /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
> + if (arm_hcr_el2_eff(env) & HCR_TPCP) {
> + return CP_ACCESS_TRAP_EL2;
> + }
> + break;
> + }
> + return CP_ACCESS_OK;
> +}
thanks
-- PMM
