Under KVM the ATS instruction will trap. Signed-off-by: Philippe Mathieu-Daudé <phi...@redhat.com> --- target/arm/helper.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c index 924deffd65..a5280c091b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3322,7 +3322,7 @@ static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) } } -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* get_phys_addr() isn't present for user-mode-only targets */ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3631,7 +3631,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); } -#endif +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ static const ARMCPRegInfo vapa_cp_reginfo[] = { { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, @@ -3639,7 +3639,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = { .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), offsetoflow32(CPUARMState, cp15.par_ns) }, .writefn = par_write }, -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* This underdecoding is safe because the reginfo is NO_RAW. */ { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .accessfn = ats_access, @@ -4880,7 +4880,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_alle1is_write }, -#ifndef CONFIG_USER_ONLY + +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* 64 bit address translation operations */ { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, @@ -4929,7 +4930,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .access = PL1_RW, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), .writefn = par_write }, -#endif +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ + /* TLB invalidate last level of translation table walk */ { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, @@ -5536,7 +5538,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae2is_write }, -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* Unlike the other EL2-related AT operations, these must * UNDEF from EL3 if EL2 is not implemented, which is why we * define them here rather than with the rest of the AT ops. @@ -6992,7 +6994,7 @@ static const ARMCPRegInfo vhe_reginfo[] = { REGINFO_SENTINEL }; -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) static const ARMCPRegInfo ats1e1_reginfo[] = { { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, @@ -7894,14 +7896,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pan, cpu)) { define_one_arm_cp_reg(cpu, &pan_reginfo); } -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) if (cpu_isar_feature(aa64_ats1e1, cpu)) { define_arm_cp_regs(cpu, ats1e1_reginfo); } if (cpu_isar_feature(aa32_ats1e1, cpu)) { define_arm_cp_regs(cpu, ats1cp_reginfo); } -#endif +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ if (cpu_isar_feature(aa64_uao, cpu)) { define_one_arm_cp_reg(cpu, &uao_reginfo); } -- 2.21.1