All of those, and tbl, tbx, ins, are fixed in the three subsequent

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  AArch64 EXT instruction for V register does not clear MSB side bits

Status in QEMU:
  Fix Committed

Bug description:
  On AArch64 CPU with SVE register, there seems to be a bug in the
  operation when executing EXT instruction to V registers. Bits above
  the 128 bits of the SVE register must be cleared to 0, but qemu-
  aarch64 seems to hold the value.

  ext v0.16b, v1.16b v2.16b, 8

  After executing above instruction, (N-1) to 128 bits of z0 register
  must be 0, where N is SVE register width.

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