On Wed, Mar 25, 2020 at 12:22 PM Philippe Mathieu-Daudé <f4...@amsat.org> wrote:
>
> Patch created mechanically by running:
>
> $ spatch \
> --macro-file scripts/cocci-macro-file.h --include-headers \
> --sp-file
> scripts/coccinelle/object_property_missing_error_propagate.cocci \
> --keep-comments --smpl-spacing --in-place --dir hw
>
> Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> hw/arm/stm32f205_soc.c | 4 ++++
> hw/arm/stm32f405_soc.c | 4 ++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
> index 118c342559..1d80f91dd7 100644
> --- a/hw/arm/stm32f205_soc.c
> +++ b/hw/arm/stm32f205_soc.c
> @@ -83,113 +83,117 @@ static void stm32f205_soc_initfn(Object *obj)
> static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
> {
> STM32F205State *s = STM32F205_SOC(dev_soc);
> DeviceState *dev, *armv7m;
> SysBusDevice *busdev;
> Error *err = NULL;
> int i;
>
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *sram = g_new(MemoryRegion, 1);
> MemoryRegion *flash = g_new(MemoryRegion, 1);
> MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
>
> memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F205.flash",
> FLASH_SIZE, &error_fatal);
> memory_region_init_alias(flash_alias, OBJECT(dev_soc),
> "STM32F205.flash.alias", flash, 0, FLASH_SIZE);
>
> memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
> memory_region_add_subregion(system_memory, 0, flash_alias);
>
> memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
> &error_fatal);
> memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
>
> armv7m = DEVICE(&s->armv7m);
> qdev_prop_set_uint32(armv7m, "num-irq", 96);
> qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
> qdev_prop_set_bit(armv7m, "enable-bitband", true);
> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
> "memory", &error_abort);
> object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
>
> /* System configuration controller */
> dev = DEVICE(&s->syscfg);
> object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> busdev = SYS_BUS_DEVICE(dev);
> sysbus_mmio_map(busdev, 0, 0x40013800);
> sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
>
> /* Attach UART (uses USART registers) and USART controllers */
> for (i = 0; i < STM_NUM_USARTS; i++) {
> dev = DEVICE(&(s->usart[i]));
> qdev_prop_set_chr(dev, "chardev", serial_hd(i));
> object_property_set_bool(OBJECT(&s->usart[i]), true, "realized",
> &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> busdev = SYS_BUS_DEVICE(dev);
> sysbus_mmio_map(busdev, 0, usart_addr[i]);
> sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m,
> usart_irq[i]));
> }
>
> /* Timer 2 to 5 */
> for (i = 0; i < STM_NUM_TIMERS; i++) {
> dev = DEVICE(&(s->timer[i]));
> qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
> object_property_set_bool(OBJECT(&s->timer[i]), true, "realized",
> &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> busdev = SYS_BUS_DEVICE(dev);
> sysbus_mmio_map(busdev, 0, timer_addr[i]);
> sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m,
> timer_irq[i]));
> }
>
> /* ADC 1 to 3 */
> object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
> "num-lines", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
> qdev_get_gpio_in(armv7m, ADC_IRQ));
>
> for (i = 0; i < STM_NUM_ADCS; i++) {
> dev = DEVICE(&(s->adc[i]));
> object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> busdev = SYS_BUS_DEVICE(dev);
> sysbus_mmio_map(busdev, 0, adc_addr[i]);
> sysbus_connect_irq(busdev, 0,
> qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
> }
>
> /* SPI 1 and 2 */
> for (i = 0; i < STM_NUM_SPIS; i++) {
> dev = DEVICE(&(s->spi[i]));
> object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> busdev = SYS_BUS_DEVICE(dev);
> sysbus_mmio_map(busdev, 0, spi_addr[i]);
> sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
> }
> }
> diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
> index 4f10ce6176..398a3b5b4f 100644
> --- a/hw/arm/stm32f405_soc.c
> +++ b/hw/arm/stm32f405_soc.c
> @@ -89,183 +89,187 @@ static void stm32f405_soc_initfn(Object *obj)
> static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
> {
> STM32F405State *s = STM32F405_SOC(dev_soc);
> MemoryRegion *system_memory = get_system_memory();
> DeviceState *dev, *armv7m;
> SysBusDevice *busdev;
> Error *err = NULL;
> int i;
>
> memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash",
> FLASH_SIZE, &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
> "STM32F405.flash.alias", &s->flash, 0,
> FLASH_SIZE);
>
> memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS,
> &s->flash);
> memory_region_add_subregion(system_memory, 0, &s->flash_alias);
>
> memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE,
> &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
>
> armv7m = DEVICE(&s->armv7m);
> qdev_prop_set_uint32(armv7m, "num-irq", 96);
> qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
> qdev_prop_set_bit(armv7m, "enable-bitband", true);
> object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory),
> "memory", &error_abort);
> object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
>
> /* System configuration controller */
> dev = DEVICE(&s->syscfg);
> object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> busdev = SYS_BUS_DEVICE(dev);
> sysbus_mmio_map(busdev, 0, SYSCFG_ADD);
> sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ));
>
> /* Attach UART (uses USART registers) and USART controllers */
> for (i = 0; i < STM_NUM_USARTS; i++) {
> dev = DEVICE(&(s->usart[i]));
> qdev_prop_set_chr(dev, "chardev", serial_hd(i));
> object_property_set_bool(OBJECT(&s->usart[i]), true, "realized",
> &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> busdev = SYS_BUS_DEVICE(dev);
> sysbus_mmio_map(busdev, 0, usart_addr[i]);
> sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m,
> usart_irq[i]));
> }
>
> /* Timer 2 to 5 */
> for (i = 0; i < STM_NUM_TIMERS; i++) {
> dev = DEVICE(&(s->timer[i]));
> qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
> object_property_set_bool(OBJECT(&s->timer[i]), true, "realized",
> &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> busdev = SYS_BUS_DEVICE(dev);
> sysbus_mmio_map(busdev, 0, timer_addr[i]);
> sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m,
> timer_irq[i]));
> }
>
> /* ADC device, the IRQs are ORed together */
> object_initialize_child(OBJECT(s), "adc-orirq", &s->adc_irqs,
> sizeof(s->adc_irqs), TYPE_OR_IRQ,
> &err, NULL);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS,
> "num-lines", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
> qdev_get_gpio_in(armv7m, ADC_IRQ));
>
> dev = DEVICE(&(s->adc[i]));
> object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> busdev = SYS_BUS_DEVICE(dev);
> sysbus_mmio_map(busdev, 0, ADC_ADDR);
> sysbus_connect_irq(busdev, 0,
> qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
>
> /* SPI devices */
> for (i = 0; i < STM_NUM_SPIS; i++) {
> dev = DEVICE(&(s->spi[i]));
> object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> busdev = SYS_BUS_DEVICE(dev);
> sysbus_mmio_map(busdev, 0, spi_addr[i]);
> sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
> }
>
> /* EXTI device */
> dev = DEVICE(&s->exti);
> object_property_set_bool(OBJECT(&s->exti), true, "realized", &err);
> if (err != NULL) {
> error_propagate(errp, err);
> return;
> }
> busdev = SYS_BUS_DEVICE(dev);
> sysbus_mmio_map(busdev, 0, EXTI_ADDR);
> for (i = 0; i < 16; i++) {
> sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
> }
> for (i = 0; i < 16; i++) {
> qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev,
> i));
> }
>
> create_unimplemented_device("timer[7]", 0x40001400, 0x400);
> create_unimplemented_device("timer[12]", 0x40001800, 0x400);
> create_unimplemented_device("timer[6]", 0x40001000, 0x400);
> create_unimplemented_device("timer[13]", 0x40001C00, 0x400);
> create_unimplemented_device("timer[14]", 0x40002000, 0x400);
> create_unimplemented_device("RTC and BKP", 0x40002800, 0x400);
> create_unimplemented_device("WWDG", 0x40002C00, 0x400);
> create_unimplemented_device("IWDG", 0x40003000, 0x400);
> create_unimplemented_device("I2S2ext", 0x40003000, 0x400);
> create_unimplemented_device("I2S3ext", 0x40004000, 0x400);
> create_unimplemented_device("I2C1", 0x40005400, 0x400);
> create_unimplemented_device("I2C2", 0x40005800, 0x400);
> create_unimplemented_device("I2C3", 0x40005C00, 0x400);
> create_unimplemented_device("CAN1", 0x40006400, 0x400);
> create_unimplemented_device("CAN2", 0x40006800, 0x400);
> create_unimplemented_device("PWR", 0x40007000, 0x400);
> create_unimplemented_device("DAC", 0x40007400, 0x400);
> create_unimplemented_device("timer[1]", 0x40010000, 0x400);
> create_unimplemented_device("timer[8]", 0x40010400, 0x400);
> create_unimplemented_device("SDIO", 0x40012C00, 0x400);
> create_unimplemented_device("timer[9]", 0x40014000, 0x400);
> create_unimplemented_device("timer[10]", 0x40014400, 0x400);
> create_unimplemented_device("timer[11]", 0x40014800, 0x400);
> create_unimplemented_device("GPIOA", 0x40020000, 0x400);
> create_unimplemented_device("GPIOB", 0x40020400, 0x400);
> create_unimplemented_device("GPIOC", 0x40020800, 0x400);
> create_unimplemented_device("GPIOD", 0x40020C00, 0x400);
> create_unimplemented_device("GPIOE", 0x40021000, 0x400);
> create_unimplemented_device("GPIOF", 0x40021400, 0x400);
> create_unimplemented_device("GPIOG", 0x40021800, 0x400);
> create_unimplemented_device("GPIOH", 0x40021C00, 0x400);
> create_unimplemented_device("GPIOI", 0x40022000, 0x400);
> create_unimplemented_device("CRC", 0x40023000, 0x400);
> create_unimplemented_device("RCC", 0x40023800, 0x400);
> create_unimplemented_device("Flash Int", 0x40023C00, 0x400);
> create_unimplemented_device("BKPSRAM", 0x40024000, 0x400);
> create_unimplemented_device("DMA1", 0x40026000, 0x400);
> create_unimplemented_device("DMA2", 0x40026400, 0x400);
> create_unimplemented_device("Ethernet", 0x40028000, 0x1400);
> create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000);
> create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000);
> create_unimplemented_device("DCMI", 0x50050000, 0x400);
> create_unimplemented_device("RNG", 0x50060800, 0x400);
> }
> --
> 2.21.1
>
>
