On Mon, Apr 27, 2020 at 1:11 PM Amanieu d'Antras <aman...@gmail.com> wrote: > > These now match the field layout used by the kernel. > > Signed-off-by: Amanieu d'Antras <aman...@gmail.com>
Thanks for the patch! Unfortunately this fixed has already been applied to the RISC-V tree (https://github.com/alistair23/qemu/tree/riscv-to-apply) and will be merged once the 5.1 development window opens up. Alistair > --- > linux-user/riscv/signal.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c > index 83ecc6f799..2b15e32a7b 100644 > --- a/linux-user/riscv/signal.c > +++ b/linux-user/riscv/signal.c > @@ -32,7 +32,7 @@ > struct target_sigcontext { > abi_long pc; > abi_long gpr[31]; /* x0 is not present, so all offsets must be -1 */ > - uint64_t fpr[32]; > + uint64_t fpr[32] __attribute__((aligned(16))); > uint32_t fcsr; > }; /* cf. riscv-linux:arch/riscv/include/uapi/asm/ptrace.h */ > > @@ -40,8 +40,9 @@ struct target_ucontext { > unsigned long uc_flags; > struct target_ucontext *uc_link; > target_stack_t uc_stack; > - struct target_sigcontext uc_mcontext; > target_sigset_t uc_sigmask; > + char __unused[1024 / 8 - sizeof(target_sigset_t)]; > + struct target_sigcontext uc_mcontext; > }; > > struct target_rt_sigframe { > -- > 2.26.1 > >