Re: [RFC PATCH 1/8] riscv: Add RV64I instructions description

[LIU Zhiwei]

On 2020/5/12 0:39, Richard Henderson wrote:
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
+LUI RISCV imm:20 rd:5 0110111 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
I think it would be helpful to add a function for this.  e.g. greg($rd) and
gbase($rs1) (including $0).  It would keep the constraints smaller, and avoid
mistakes.

These functions would go into risugen_riscv.pm.
Good idea. I will take it next patch set.
+ADDI RISCV imm:12 rs1:5 000 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
Since all of sp, gp, tp are not in risu's control, why is rs1 only excluding
sp, and not gp and tp as well?
When I test the patch set, I find gp and tp will be the same in slave 
and master，
so they can be used as source register.

I will check it again in next patch set test.

Zhiwei

r~