On Thu, May 21, 2020 at 4:19 AM LIU Zhiwei <zhiwei_...@c-sky.com> wrote: > > Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com> > Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/helper.h | 7 +++++++ > target/riscv/insn32.decode | 2 ++ > target/riscv/insn_trans/trans_rvv.inc.c | 4 ++++ > target/riscv/vector_helper.c | 11 +++++++++++ > 4 files changed, 24 insertions(+) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 93a7a303ee..ce31577ea9 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -1066,3 +1066,10 @@ DEF_HELPER_6(vredxor_vs_b, void, ptr, ptr, ptr, ptr, > env, i32) > DEF_HELPER_6(vredxor_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vredxor_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vredxor_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > + > +DEF_HELPER_6(vwredsumu_vs_b, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwredsumu_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwredsumu_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 773b32f0b4..b69d804fda 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -537,6 +537,8 @@ vredminu_vs 000100 . ..... ..... 010 ..... 1010111 > @r_vm > vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm > vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm > vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm > +vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm > +vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm > > vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > diff --git a/target/riscv/insn_trans/trans_rvv.inc.c > b/target/riscv/insn_trans/trans_rvv.inc.c > index 9dfb9358a2..8d75b3ca84 100644 > --- a/target/riscv/insn_trans/trans_rvv.inc.c > +++ b/target/riscv/insn_trans/trans_rvv.inc.c > @@ -2333,3 +2333,7 @@ GEN_OPIVV_TRANS(vredmin_vs, reduction_check) > GEN_OPIVV_TRANS(vredand_vs, reduction_check) > GEN_OPIVV_TRANS(vredor_vs, reduction_check) > GEN_OPIVV_TRANS(vredxor_vs, reduction_check) > + > +/* Vector Widening Integer Reduction Instructions */ > +GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check) > +GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check) > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 00ed6a75a5..5035e0bb0e 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -4405,3 +4405,14 @@ GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, > DO_XOR, clearb) > GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh) > GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl) > GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq) > + > +/* Vector Widening Integer Reduction Instructions */ > +/* signed sum reduction into double-width accumulator */ > +GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD, clearh) > +GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD, clearl) > +GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq) > + > +/* Unsigned sum reduction into double-width accumulator */ > +GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh) > +GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl) > +GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq) > -- > 2.23.0 > >