On 6/4/20 7:50 PM, LIU Zhiwei wrote:
> So no scalar insns will require changes within a translation block.
Not true -- scalar insns can encode rm into the instruction.
> I think there is a error in gen_set_rm
>
> static void gen_set_rm(DisasContext *ctx, int rm)
> {
> TCGv_i32 t0;
>
> if (ctx->frm == rm) {
> return;
> }
> ctx->frm = rm;
> t0 = tcg_const_i32(rm);
> gen_helper_set_rounding_mode(cpu_env, t0);
> tcg_temp_free_i32(t0);
> }
>
> I don't know why updating ctx->frm in this function.
This is a cache of the current rm, as most recently stored in
env->fp_status.rounding_mode.
So if we have
fadd.s ft0, ft0, ft0, rtz
fadd.s ft0, ft0, ft0, rtz
fadd.s ft0, ft0, ft0, rtz
we will only switch to round_to_zero once.
r~
