On Wed, 8 Jul 2020 at 15:20, Eric Auger <eric.au...@redhat.com> wrote: > > Add the support for AIDR register. It currently advertises > SMMU V3.0 spec. > > Signed-off-by: Eric Auger <eric.au...@redhat.com> > > --- > --- > hw/arm/smmuv3-internal.h | 1 + > include/hw/arm/smmuv3.h | 1 + > hw/arm/smmuv3.c | 3 +++ > 3 files changed, 5 insertions(+) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index ef093eaff5..6296235020 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -64,6 +64,7 @@ REG32(IDR5, 0x14) > #define SMMU_IDR5_OAS 4 > > REG32(IIDR, 0x18) > +REG32(AIDR, 0x1C)
Rest of file uses lowercase letters for hex values, so "0x1c". > REG32(CR0, 0x20) > FIELD(CR0, SMMU_ENABLE, 0, 1) > FIELD(CR0, EVENTQEN, 2, 1) Otherwise Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
