On 7/22/20 2:16 AM, frank.ch...@sifive.com wrote:
> +/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */
> +static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a)
> +{
> + if (require_rvv(s) &&
> + vext_check_isa_ill(s)) {
> + TCGv_i64 t1;
> + TCGv dest;
> +
> + t1 = tcg_temp_new_i64();
> + dest = tcg_temp_new();
> + /*
> + * load vreg and sign-extend to 64 bits,
> + * then truncate to XLEN bits before storing to gpr.
> + */
> + vec_element_loadi(s, t1, a->rs2, 0, true);
> + tcg_gen_trunc_i64_tl(dest, t1);
> + gen_set_gpr(a->rd, dest);
> + tcg_temp_free_i64(t1);
> + tcg_temp_free(dest);
> + mark_vs_dirty(s);
No need to mark the vector set dirty, since we're modifying general regs.
Otherwise,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
