Re: [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions

[Richard Henderson]

On 7/22/20 2:16 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang <frank.ch...@sifive.com>
> 
> Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
> 
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
> ---
>  target/riscv/insn_trans/trans_rvv.inc.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Richard Henderson <richard.hender...@linaro.org>

r~