The spec is a draft but required by vector extension. The reference is availabe at https://github.com/riscv/riscv-isa-manual/tree/zfh
The patch depends two unmerged patch set 1. extend softfloat to support int8 and alternative NaN probagapation 2. NaNBox fix Based-on: <1596102747-20226-1-git-send-email-chihmin.c...@sifive.com> Based-on: <20200724002807.441147-1-richard.hender...@linaro.org> Chih-Min Chao (2): target/riscv: add NaN-Boxing helper for half-float target/riscv: support 'x-k' in cpu option Kito Cheng (1): target/riscv: Implement zfh extension target/riscv/cpu.c | 4 + target/riscv/cpu.h | 2 + target/riscv/fpu_helper.c | 180 ++++++++++ target/riscv/helper.h | 34 ++ target/riscv/insn32-64.decode | 6 + target/riscv/insn32.decode | 32 ++ target/riscv/insn_trans/trans_rvzfh.inc.c | 531 ++++++++++++++++++++++++++++++ target/riscv/internals.h | 16 + target/riscv/translate.c | 16 + 9 files changed, 821 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzfh.inc.c -- 2.7.4
