First arm pullreq for 5.2: Eric's SMMU stuff, and a bunch of cleanup/refactoring from me.
thanks -- PMM The following changes since commit 8367a77c4d3f6e1e60890f5510304feb2c621611: Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.2-pull-request' into staging (2020-08-23 16:34:43 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200824 for you to fetch changes up to b34aa5129e9c3aff890b4f4bcc84962e94185629: target/arm: Use correct FPST for VCMLA, VCADD on fp16 (2020-08-24 10:15:12 +0100) ---------------------------------------------------------------- target-arm queue: * hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores * hw/arm/smmuv3: Implement SMMUv3.2 range-invalidation * docs/system/arm: Document the Xilinx Versal Virt board * target/arm: Make M-profile NOCP take precedence over UNDEF * target/arm: Use correct FPST for VCMLA, VCADD on fp16 * target/arm: Various cleanups preparing for fp16 support ---------------------------------------------------------------- Edgar E. Iglesias (1): docs/system/arm: Document the Xilinx Versal Virt board Eric Auger (11): hw/arm/smmu-common: Factorize some code in smmu_ptw_64() hw/arm/smmu-common: Add IOTLB helpers hw/arm/smmu: Introduce smmu_get_iotlb_key() hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value hw/arm/smmu-common: Manage IOTLB block entries hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper hw/arm/smmuv3: Get prepared for range invalidation hw/arm/smmuv3: Fix IIDR offset hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation Peter Maydell (14): target/arm: Pull handling of XScale insns out of disas_coproc_insn() target/arm: Separate decode from handling of coproc insns target/arm: Convert A32 coprocessor insns to decodetree target/arm: Tidy up disas_arm_insn() target/arm: Do M-profile NOCP checks early and via decodetree target/arm: Convert T32 coprocessor insns to decodetree target/arm: Remove ARCH macro target/arm: Delete unused VFP_DREG macros target/arm/translate.c: Delete/amend incorrect comments target/arm: Delete unused ARM_FEATURE_CRC target/arm: Replace A64 get_fpstatus_ptr() with generic fpstatus_ptr() target/arm: Make A32/T32 use new fpstatus_ptr() API target/arm: Implement FPST_STD_F16 fpstatus target/arm: Use correct FPST for VCMLA, VCADD on fp16 Philippe Mathieu-Daudé (1): hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores docs/system/arm/xlnx-versal-virt.rst | 176 +++++++++++++++++++++++ docs/system/target-arm.rst | 1 + hw/arm/smmu-internal.h | 8 ++ hw/arm/smmuv3-internal.h | 10 +- include/hw/arm/smmu-common.h | 19 ++- include/hw/arm/smmuv3.h | 1 + target/arm/cpu.h | 10 +- target/arm/translate-a64.h | 1 - target/arm/translate.h | 52 +++++++ target/arm/a32.decode | 19 +++ target/arm/m-nocp.decode | 42 ++++++ target/arm/t32.decode | 19 +++ target/arm/vfp.decode | 2 - hw/arm/smmu-common.c | 214 ++++++++++++++++++--------- hw/arm/smmuv3.c | 142 +++++++++--------- hw/cpu/a9mpcore.c | 12 +- target/arm/cpu.c | 3 + target/arm/helper.c | 29 ++++ target/arm/translate-a64.c | 89 +++++------- target/arm/translate-sve.c | 34 ++--- target/arm/translate.c | 272 +++++++++++++++++------------------ target/arm/vfp_helper.c | 5 + MAINTAINERS | 3 +- hw/arm/trace-events | 12 +- target/arm/meson.build | 1 + target/arm/translate-neon.c.inc | 28 ++-- target/arm/translate-vfp.c.inc | 96 ++++++++----- 27 files changed, 885 insertions(+), 415 deletions(-) create mode 100644 docs/system/arm/xlnx-versal-virt.rst create mode 100644 target/arm/m-nocp.decode
