On 08/26/20 13:55, Igor Mammedov wrote: > On Wed, 26 Aug 2020 11:24:14 +0200 > Laszlo Ersek <ler...@redhat.com> wrote:
>> (2a) Change the firmware so that it sends a directed SMI as well to >> each CPU, just before sending an INIT-SIPI-SIPI. This should be >> idempotent -- if the broadcast SMI *has* covered the the CPU, >> then sending a directed SMI should make no difference. > may be still racy, as new cpus can arrive diring/after direct broadcast. (I think you meant "direct SMI") That's not a problem -- the point is that we must never send INIT-SIPI-SIPI to a hot-added CPU without making an SMI pending for it. The above condition can be satisfied by not sending INIT-SIPI-SIPI to a VCPU at all. The firmware collects pending CPUs into an array, and then does the directed SMI + INIT-SIPI-SIPI dance for each, in a separate loop. So if a new VCPU is hot-added while we are sending the interrupts to the already collected ones, that's fine -- we're not going to send *either* SMI *or* INIT-SIPI-SIPI to that VCPU, until the next time we collect VCPUS. It's basically the same idea as in your ACPI patch for QEMU. I'll send the OVMF patches soon. Thanks! Laszlo
