From: Jagannathan Raman <jag.ra...@oracle.com>
Proxy device object implements handler for PCI BAR writes and reads.
The handler uses BAR_WRITE/BAR_READ message to communicate to the
remote process with the BAR address and value to be written/read.
The remote process implements handler for BAR_WRITE/BAR_READ
message.
Signed-off-by: Jagannathan Raman <jag.ra...@oracle.com>
Signed-off-by: Elena Ufimtseva <elena.ufimts...@oracle.com>
Signed-off-by: John G Johnson <john.g.john...@oracle.com>
---
hw/i386/remote-msg.c | 94 ++++++++++++++++++++++++++++++++++++++++
hw/pci/proxy.c | 64 ++++++++++++++++++++++++++-
include/hw/pci/proxy.h | 16 ++++++-
include/io/mpqemu-link.h | 10 +++++
io/mpqemu-link.c | 6 +++
5 files changed, 186 insertions(+), 4 deletions(-)
diff --git a/hw/i386/remote-msg.c b/hw/i386/remote-msg.c
index 322c1888a3..841c681d76 100644
--- a/hw/i386/remote-msg.c
+++ b/hw/i386/remote-msg.c
@@ -16,11 +16,14 @@
#include "qapi/error.h"
#include "sysemu/runstate.h"
#include "hw/pci/pci.h"
+#include "exec/memattrs.h"
static void process_config_write(QIOChannel *ioc, PCIDevice *dev,
MPQemuMsg *msg);
static void process_config_read(QIOChannel *ioc, PCIDevice *dev,
MPQemuMsg *msg);
+static void process_bar_write(QIOChannel *ioc, MPQemuMsg *msg, Error **errp);
+static void process_bar_read(QIOChannel *ioc, MPQemuMsg *msg, Error **errp);
gboolean mpqemu_process_msg(QIOChannel *ioc, GIOCondition cond,
gpointer opaque)
@@ -62,6 +65,12 @@ gboolean mpqemu_process_msg(QIOChannel *ioc, GIOCondition
cond,
case PCI_CONFIG_READ:
process_config_read(ioc, pci_dev, &msg);
break;
+ case BAR_WRITE:
+ process_bar_write(ioc, &msg, &local_err);
+ break;
+ case BAR_READ:
+ process_bar_read(ioc, &msg, &local_err);
+ break;
default:
error_setg(&local_err,
"Unknown command (%d) received for device %s (pid=%d)",
@@ -134,3 +143,88 @@ static void process_config_read(QIOChannel *ioc, PCIDevice
*dev,
getpid());
}
}
+
+static void process_bar_write(QIOChannel *ioc, MPQemuMsg *msg, Error **errp)
+{
+ BarAccessMsg *bar_access = &msg->data.bar_access;
+ AddressSpace *as =
+ bar_access->memory ? &address_space_memory : &address_space_io;
+ MPQemuMsg ret = { 0 };
+ MPQemuRequest req = { 0 };
+ MemTxResult res;
+ uint64_t val;
+ Error *local_err = NULL;
+
+ if (!is_power_of_2(bar_access->size) ||
+ (bar_access->size > sizeof(uint64_t))) {
+ ret.data.u64 = UINT64_MAX;
+ goto fail;
+ }
+
+ val = cpu_to_le64(bar_access->val);
+
+ res = address_space_rw(as, bar_access->addr, MEMTXATTRS_UNSPECIFIED,
+ (void *)&val, bar_access->size, true);
+
+ if (res != MEMTX_OK) {
+ error_setg(errp, "Could not perform address space write operation,"
+ " inaccessible address: %lx in pid %d.",
+ bar_access->addr, getpid());
+ ret.data.u64 = -1;
+ }
+
+fail:
+ ret.cmd = RET_MSG;
+ ret.size = sizeof(ret.data.u64);
+
+ req.ioc = ioc;
+ req.msg = &ret;
+
+ mpqemu_msg_send_in_co(&req, ioc, (errp && *errp) ? NULL : &local_err);
+ if (local_err) {
+ error_setg(errp, "Error while sending message to proxy "
+ "in remote process pid=%d", getpid());
+ }
+}
+
+static void process_bar_read(QIOChannel *ioc, MPQemuMsg *msg, Error **errp)
+{
+ BarAccessMsg *bar_access = &msg->data.bar_access;
+ MPQemuMsg ret = { 0 };
+ MPQemuRequest req = { 0 };
+ AddressSpace *as;
+ MemTxResult res;
+ uint64_t val = 0;
+ Error *local_err = NULL;
+
+ as = bar_access->memory ? &address_space_memory : &address_space_io;
+
+ if (!is_power_of_2(bar_access->size) ||
+ (bar_access->size > sizeof(uint64_t))) {
+ val = UINT64_MAX;
+ goto fail;
+ }
+
+ res = address_space_rw(as, bar_access->addr, MEMTXATTRS_UNSPECIFIED,
+ (void *)&val, bar_access->size, false);
+
+ if (res != MEMTX_OK) {
+ error_setg(errp, "Could not perform address space read operation,"
+ " inaccessible address: %lx in pid %d.",
+ bar_access->addr, getpid());
+ val = UINT64_MAX;
+ }
+
+fail:
+ ret.cmd = RET_MSG;
+ ret.data.u64 = le64_to_cpu(val);
+ ret.size = sizeof(ret.data.u64);
+
+ req.ioc = ioc;
+ req.msg = &ret;
+ mpqemu_msg_send_in_co(&req, ioc, (errp && *errp) ? NULL : &local_err);
+ if (local_err) {
+ error_setg(errp, "Error while sending message to proxy "
+ "in remote process pid=%d", getpid());
+ }
+}
diff --git a/hw/pci/proxy.c b/hw/pci/proxy.c
index 23aab44d8e..d332c63bf3 100644
--- a/hw/pci/proxy.c
+++ b/hw/pci/proxy.c
@@ -61,7 +61,7 @@ static int config_op_send(PCIProxyDev *pdev, uint32_t addr,
uint32_t *val,
int l, unsigned int op)
{
MPQemuMsg msg = { 0 };
- long ret = -EINVAL;
+ uint64_t ret = -EINVAL;
Error *local_err = NULL;
msg.cmd = op;
@@ -72,7 +72,7 @@ static int config_op_send(PCIProxyDev *pdev, uint32_t addr,
uint32_t *val,
ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
if (local_err) {
- error_report("Failed to exchange PCI_CONFIG message with remote");
+ error_report_err(local_err);
}
if (op == PCI_CONFIG_READ) {
*val = (uint32_t)ret;
@@ -132,3 +132,63 @@ static void pci_proxy_dev_register_types(void)
}
type_init(pci_proxy_dev_register_types)
+
+static void send_bar_access_msg(PCIProxyDev *pdev, MemoryRegion *mr,
+ bool write, hwaddr addr, uint64_t *val,
+ unsigned size, bool memory)
+{
+ MPQemuMsg msg = { 0 };
+ long ret = -EINVAL;
+ Error *local_err = NULL;
+
+ msg.size = sizeof(BarAccessMsg);
+ msg.data.bar_access.addr = mr->addr + addr;
+ msg.data.bar_access.size = size;
+ msg.data.bar_access.memory = memory;
+
+ if (write) {
+ msg.cmd = BAR_WRITE;
+ msg.data.bar_access.val = *val;
+ } else {
+ msg.cmd = BAR_READ;
+ }
+
+ ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
+ if (local_err) {
+ error_report_err(local_err);
+ }
+
+ if (!write) {
+ *val = ret;
+ }
+}
+
+static void proxy_bar_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ ProxyMemoryRegion *pmr = opaque;
+
+ send_bar_access_msg(pmr->dev, &pmr->mr, true, addr, &val, size,
+ pmr->memory);
+}
+
+static uint64_t proxy_bar_read(void *opaque, hwaddr addr, unsigned size)
+{
+ ProxyMemoryRegion *pmr = opaque;
+ uint64_t val;
+
+ send_bar_access_msg(pmr->dev, &pmr->mr, false, addr, &val, size,
+ pmr->memory);
+
+ return val;
+}
+
+const MemoryRegionOps proxy_mr_ops = {
+ .read = proxy_bar_read,
+ .write = proxy_bar_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+};
diff --git a/include/hw/pci/proxy.h b/include/hw/pci/proxy.h
index 4ae7becf34..e5e18f0b15 100644
--- a/include/hw/pci/proxy.h
+++ b/include/hw/pci/proxy.h
@@ -17,7 +17,17 @@
#define PCI_PROXY_DEV(obj) \
OBJECT_CHECK(PCIProxyDev, (obj), TYPE_PCI_PROXY_DEV)
-typedef struct PCIProxyDev {
+typedef struct PCIProxyDev PCIProxyDev;
+
+typedef struct ProxyMemoryRegion {
+ PCIProxyDev *dev;
+ MemoryRegion mr;
+ bool memory;
+ bool present;
+ uint8_t type;
+} ProxyMemoryRegion;
+
+struct PCIProxyDev {
PCIDevice parent_dev;
char *fd;
@@ -29,6 +39,8 @@ typedef struct PCIProxyDev {
*/
QemuMutex io_mutex;
QIOChannel *ioc;
-} PCIProxyDev;
+
+ ProxyMemoryRegion region[PCI_NUM_REGIONS];
+};
#endif /* PROXY_H */
diff --git a/include/io/mpqemu-link.h b/include/io/mpqemu-link.h
index a0ffedcdb1..967ae24e3a 100644
--- a/include/io/mpqemu-link.h
+++ b/include/io/mpqemu-link.h
@@ -36,6 +36,8 @@ typedef enum {
RET_MSG,
PCI_CONFIG_WRITE,
PCI_CONFIG_READ,
+ BAR_WRITE,
+ BAR_READ,
MAX = INT_MAX,
} MPQemuCmd;
@@ -51,6 +53,13 @@ typedef struct {
int l;
} ConfDataMsg;
+typedef struct {
+ hwaddr addr;
+ uint64_t val;
+ unsigned size;
+ bool memory;
+} BarAccessMsg;
+
/**
* MPQemuMsg:
* @cmd: The remote command
@@ -70,6 +79,7 @@ typedef struct {
uint64_t u64;
ConfDataMsg conf_data;
SyncSysmemMsg sync_sysmem;
+ BarAccessMsg bar_access;
} data;
int fds[REMOTE_MAX_FDS];
diff --git a/io/mpqemu-link.c b/io/mpqemu-link.c
index af9f536660..9233df215e 100644
--- a/io/mpqemu-link.c
+++ b/io/mpqemu-link.c
@@ -328,6 +328,12 @@ bool mpqemu_msg_valid(MPQemuMsg *msg)
return false;
}
break;
+ case BAR_WRITE:
+ case BAR_READ:
+ if ((msg->size != sizeof(BarAccessMsg)) || (msg->num_fds != 0)) {
+ return false;
+ }
+ break;
default:
break;
}
--
2.25.GIT
