From: Igor Mammedov <imamm...@redhat.com> Spec[1] defines 0 - 3 level memory side cache, however QEMU CLI allows to specify an intermediate cache level without specifying previous level. Such option(s) silently ignored when building HMAT table, which leads to incomplete cache information. Make sure that previous level exists and error out if it hasn't been provided.
1) ACPI 6.2A 5.2.27.5 Memory Side Cache Information Structure Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1842877 Signed-off-by: Igor Mammedov <imamm...@redhat.com> Message-Id: <20200924091406.1321012-1-imamm...@redhat.com> Reviewed-by: Eduardo Habkost <ehabk...@redhat.com> Signed-off-by: Eduardo Habkost <ehabk...@redhat.com> --- hw/core/numa.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/core/numa.c b/hw/core/numa.c index 7d5d4130016..6dc3d19d282 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -424,7 +424,13 @@ void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node, } if ((node->level > 1) && - ms->numa_state->hmat_cache[node->node_id][node->level - 1] && + ms->numa_state->hmat_cache[node->node_id][node->level - 1] == NULL) { + error_setg(errp, "Cache level=%" PRIu8 " shall be defined first", + node->level - 1); + return; + } + + if ((node->level > 1) && (node->size <= ms->numa_state->hmat_cache[node->node_id][node->level - 1]->size)) { error_setg(errp, "Invalid size=%" PRIu64 ", the size of level=%" PRIu8 -- 2.26.2
