Hi all, This patch series adresses comments and suggestions from v1. I hope that I managedd to address all of them.
Thanks Alexey Baturo (4): [RISCV_PM] Add J-extension into RISC-V [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode [RISCV_PM] Print new PM CSRs in QEMU logs [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Anatoly Parshintsev (1): [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension target/riscv/cpu.c | 24 ++ target/riscv/cpu.h | 32 +++ target/riscv/cpu_bits.h | 66 ++++++ target/riscv/csr.c | 277 ++++++++++++++++++++++++ target/riscv/insn_trans/trans_rva.c.inc | 3 + target/riscv/insn_trans/trans_rvd.c.inc | 2 + target/riscv/insn_trans/trans_rvf.c.inc | 2 + target/riscv/insn_trans/trans_rvi.c.inc | 2 + target/riscv/translate.c | 49 +++++ 9 files changed, 457 insertions(+) -- 2.20.1