On Fri, 16 Oct 2020 at 22:07, Richard Henderson <richard.hender...@linaro.org> wrote: > > Since the FAR_ELx fix at 38d931687fa1, it is reported that > page granularity flushing is broken. > > This makes sense, since TCG will record the entire virtual > address in its TLB, not simply the 56 significant bits. > With no other TCG support, the ARM backend should require > 256 different page flushes to clear the virtual address of > any possible tag. > > So I added a new tcg interface that allows passing the size > of the virtual address. I thought a simple bit-count was a > cleaner interface than passing in a mask, since it means that > we couldn't be passed nonsensical masks like 0xdeadbeef. It > also makes it easy to re-direct special cases. > > Changes for v2: > * Add encode_pbm_to_runon/+decode_runon_to_pbm helpers (pmm).
Applied to target-arm.next, thanks. -- PMM
