By using scripts/checkpatch.pl, it is found that many files in hw/pci-host/
contain lines with more than 80 characters.
Signed-off-by: Gan Qixin <ganqi...@huawei.com>
---
hw/pci-host/gpex-acpi.c | 18 ++++++++----------
hw/pci-host/pam.c | 4 ++--
hw/pci-host/ppce500.c | 8 +++++---
hw/pci-host/q35.c | 11 +++++++----
hw/pci-host/versatile.c | 5 +++--
5 files changed, 25 insertions(+), 21 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index dbb350a837..a7cf59018d 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -64,12 +64,11 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
nr_pcie_buses));
if (cfg->mmio32.size) {
aml_append(rbuf,
- aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
AML_MAX_FIXED,
- AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
- cfg->mmio32.base,
+ aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
+ AML_MAX_FIXED, AML_NON_CACHEABLE,
+ AML_READ_WRITE, 0x0000, cfg->mmio32.base,
cfg->mmio32.base + cfg->mmio32.size - 1,
- 0x0000,
- cfg->mmio32.size));
+ 0x0000, cfg->mmio32.size));
}
if (cfg->pio.size) {
aml_append(rbuf,
@@ -81,12 +80,11 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
}
if (cfg->mmio64.size) {
aml_append(rbuf,
- aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
AML_MAX_FIXED,
- AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
- cfg->mmio64.base,
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
+ AML_MAX_FIXED, AML_NON_CACHEABLE,
+ AML_READ_WRITE, 0x0000, cfg->mmio64.base,
cfg->mmio64.base + cfg->mmio64.size - 1,
- 0x0000,
- cfg->mmio64.size));
+ 0x0000, cfg->mmio64.size));
}
aml_append(dev, aml_name_decl("_CRS", rbuf));
diff --git a/hw/pci-host/pam.c b/hw/pci-host/pam.c
index a496205783..6253406abd 100644
--- a/hw/pci-host/pam.c
+++ b/hw/pci-host/pam.c
@@ -45,8 +45,8 @@ void init_pam(DeviceState *dev, MemoryRegion *ram_memory,
memory_region_set_readonly(&mem->alias[1], true);
/* XXX: should distinguish read/write cases */
- memory_region_init_alias(&mem->alias[0], OBJECT(dev), "pam-pci",
pci_address_space,
- start, size);
+ memory_region_init_alias(&mem->alias[0], OBJECT(dev), "pam-pci",
+ pci_address_space, start, size);
memory_region_init_alias(&mem->alias[2], OBJECT(dev), "pam-pci",
ram_memory,
start, size);
diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c
index 9517aab913..d3e8e77236 100644
--- a/hw/pci-host/ppce500.c
+++ b/hw/pci-host/ppce500.c
@@ -423,8 +423,9 @@ static void e500_pcihost_bridge_realize(PCIDevice *d, Error
**errp)
PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
"/e500-ccsr"));
- memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0",
&ccsr->ccsr_space,
- 0, int128_get64(ccsr->ccsr_space.size));
+ memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0",
+ &ccsr->ccsr_space, 0,
+ int128_get64(ccsr->ccsr_space.size));
pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
}
@@ -474,7 +475,8 @@ static void e500_pcihost_realize(DeviceState *dev, Error
**errp)
pci_create_simple(b, 0, "e500-host-bridge");
- memory_region_init(&s->container, OBJECT(h), "pci-container",
PCIE500_ALL_SIZE);
+ memory_region_init(&s->container, OBJECT(h), "pci-container",
+ PCIE500_ALL_SIZE);
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h,
"pci-conf-idx", 4);
memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h,
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index b67cb9c29f..8c4031dda7 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -573,14 +573,17 @@ static void mch_realize(PCIDevice *d, Error **errp)
/* if *disabled* show SMRAM to all CPUs */
memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
- mch->pci_address_space,
MCH_HOST_BRIDGE_SMRAM_C_BASE,
+ mch->pci_address_space,
+ MCH_HOST_BRIDGE_SMRAM_C_BASE,
MCH_HOST_BRIDGE_SMRAM_C_SIZE);
- memory_region_add_subregion_overlap(mch->system_memory,
MCH_HOST_BRIDGE_SMRAM_C_BASE,
+ memory_region_add_subregion_overlap(mch->system_memory,
+ MCH_HOST_BRIDGE_SMRAM_C_BASE,
&mch->smram_region, 1);
memory_region_set_enabled(&mch->smram_region, true);
- memory_region_init_alias(&mch->open_high_smram, OBJECT(mch),
"smram-open-high",
- mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
+ memory_region_init_alias(&mch->open_high_smram, OBJECT(mch),
+ "smram-open-high", mch->ram_memory,
+ MCH_HOST_BRIDGE_SMRAM_C_BASE,
MCH_HOST_BRIDGE_SMRAM_C_SIZE);
memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000,
&mch->open_high_smram, 1);
diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c
index 3553277f94..1dab38e695 100644
--- a/hw/pci-host/versatile.c
+++ b/hw/pci-host/versatile.c
@@ -454,8 +454,9 @@ static void pci_vpb_realize(DeviceState *dev, Error **errp)
* offsets are guest controllable via the IMAP registers.
*/
for (i = 0; i < 3; i++) {
- memory_region_init_alias(&s->pci_mem_window[i], OBJECT(s),
"pci-vbp-window",
- &s->pci_mem_space, 0, s->mem_win_size[i]);
+ memory_region_init_alias(&s->pci_mem_window[i], OBJECT(s),
+ "pci-vbp-window", &s->pci_mem_space, 0,
+ s->mem_win_size[i]);
sysbus_init_mmio(sbd, &s->pci_mem_window[i]);
}
--
2.23.0
