The following changes since commit 4c5b97bfd0dd54dc27717ae8d1cd10e14eef1430:
Merge remote-tracking branch
'remotes/kraxel/tags/modules-20201022-pull-request' into staging (2020-10-22
12:33:21 +0100)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201023
for you to fetch changes up to 51b6c1bbc3dd1b139a9e9b021d87bcfd7d82299e:
hw/misc/sifive_u_otp: Add backend drive support (2020-10-22 12:00:50 -0700)
----------------------------------------------------------------
A collection of RISC-V fixes for the next QEMU release.
This includes:
- Improvements to logging output
- Hypervisor instruction fixups
- The ability to load a noMMU kernel
- SiFive OTP support
----------------------------------------------------------------
Alistair Francis (5):
riscv: Convert interrupt logs to use qemu_log_mask()
hw/riscv: sifive_u: Allow specifying the CPU
hw/riscv: Return the end address of the loaded firmware
hw/riscv: Add a riscv_is_32_bit() function
hw/riscv: Load the kernel after the firmware
Bin Meng (1):
hw/intc: Move sifive_plic.h to the include directory
Georg Kotheimer (3):
target/riscv: Fix update of hstatus.SPVP
target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt
target/riscv: Fix implementation of HLVX.WU instruction
Green Wan (2):
hw/misc/sifive_u_otp: Add write function and write-once protection
hw/misc/sifive_u_otp: Add backend drive support
Yifei Jiang (1):
target/riscv: raise exception to HS-mode at get_physical_address
{hw => include/hw}/intc/sifive_plic.h | 0
include/hw/misc/sifive_u_otp.h | 5 ++
include/hw/riscv/boot.h | 13 +++--
include/hw/riscv/sifive_u.h | 1 +
target/riscv/cpu.h | 10 ++--
hw/misc/sifive_u_otp.c | 95 ++++++++++++++++++++++++++++++++++-
hw/riscv/boot.c | 56 +++++++++++++++------
hw/riscv/opentitan.c | 3 +-
hw/riscv/sifive_e.c | 3 +-
hw/riscv/sifive_u.c | 28 ++++++++---
hw/riscv/spike.c | 11 ++--
hw/riscv/virt.c | 11 ++--
target/riscv/cpu_helper.c | 50 +++++++++++++-----
target/riscv/op_helper.c | 7 ++-
14 files changed, 238 insertions(+), 55 deletions(-)
rename {hw => include/hw}/intc/sifive_plic.h (100%)
