On 10/31/20 6:25 PM, Joelle van Dyne wrote: > Another thing, for x86 (and maybe other archs), the icache is cache > coherent but does it apply if we are aliasing the memory address? I > think in that case, it's like we're doing a DMA right and still need > to do flushing+invalidating?
No, it is not like dma. The x86 caches are physically tagged, so virtual aliasing does not matter. r~
