On Wed, Nov 11, 2020 at 11:51 PM Vitaly Wool <vitaly.w...@konsulko.com> wrote:
>
> Add QSPI NOR flash definition for Microchip PolarFire SoC.
>
> Signed-off-by: Vitaly Wool <vitaly.w...@konsulko.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/riscv/microchip_pfsoc.c | 21 +++++++++++++++++++++
> include/hw/riscv/microchip_pfsoc.h | 3 +++
> 2 files changed, 24 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 37ac46a1af..e952b49e8c 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -113,6 +113,8 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
> [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
> [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
> + [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 },
> + [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 },
> [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
> [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
> [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
> @@ -121,6 +123,7 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> + [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
> [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
> [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
> [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
> @@ -185,6 +188,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
> Error **errp)
> MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> MemoryRegion *envm_data = g_new(MemoryRegion, 1);
> + MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
> char *plic_hart_config;
> size_t plic_hart_config_len;
> NICInfo *nd;
> @@ -344,6 +348,14 @@ static void microchip_pfsoc_soc_realize(DeviceState
> *dev, Error **errp)
> qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
> serial_hd(4));
>
> + /* SPI */
> + create_unimplemented_device("microchip.pfsoc.spi0",
> + memmap[MICROCHIP_PFSOC_SPI0].base,
> + memmap[MICROCHIP_PFSOC_SPI0].size);
> + create_unimplemented_device("microchip.pfsoc.spi1",
> + memmap[MICROCHIP_PFSOC_SPI1].base,
> + memmap[MICROCHIP_PFSOC_SPI1].size);
> +
> /* I2C1 */
> create_unimplemented_device("microchip.pfsoc.i2c1",
> memmap[MICROCHIP_PFSOC_I2C1].base,
> @@ -401,6 +413,15 @@ static void microchip_pfsoc_soc_realize(DeviceState
> *dev, Error **errp)
> sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
> memmap[MICROCHIP_PFSOC_IOSCB].base);
> +
> + /* QSPI Flash */
> + memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
> + "microchip.pfsoc.qspi_xip",
> + memmap[MICROCHIP_PFSOC_QSPI_XIP].size,
> + &error_fatal);
> + memory_region_add_subregion(system_memory,
> + memmap[MICROCHIP_PFSOC_QSPI_XIP].base,
> + qspi_xip_mem);
> }
>
> static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/riscv/microchip_pfsoc.h
> b/include/hw/riscv/microchip_pfsoc.h
> index 51d44637db..d0c666aae0 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -97,6 +97,8 @@ enum {
> MICROCHIP_PFSOC_MMUART2,
> MICROCHIP_PFSOC_MMUART3,
> MICROCHIP_PFSOC_MMUART4,
> + MICROCHIP_PFSOC_SPI0,
> + MICROCHIP_PFSOC_SPI1,
> MICROCHIP_PFSOC_I2C1,
> MICROCHIP_PFSOC_GEM0,
> MICROCHIP_PFSOC_GEM1,
> @@ -105,6 +107,7 @@ enum {
> MICROCHIP_PFSOC_GPIO2,
> MICROCHIP_PFSOC_ENVM_CFG,
> MICROCHIP_PFSOC_ENVM_DATA,
> + MICROCHIP_PFSOC_QSPI_XIP,
> MICROCHIP_PFSOC_IOSCB,
> MICROCHIP_PFSOC_DRAM_LO,
> MICROCHIP_PFSOC_DRAM_LO_ALIAS,
> --
> 2.20.1
>
>
