On 11/25/20 3:49 AM, Joel Stanley wrote:
> On Fri, 20 Nov 2020 at 16:16, Cédric Le Goater <c...@kaod.org> wrote:
>>
>> The controller has a set of hidden bits to request/grant DMA access.
>
> Do you have the ast2600 datasheet? It describes these bits:
>
> 31 RW DMA Request
>
> Write SPIR80 = 0xAEED0000 to set this bit ot '1'.
> And hardware will clear the request to '0' after DMA done, or FW can
> clear to '0' by writing SPIR80 = 0xDEEA0000.
>
> 30 RO DMA Grant
>
> 0: DMA is not allowed to be used. All DMA related control registers
> are not allowed to be written.
> 1: DMA is granted to be used.
I see them now :) They are under the SPI controllers but not under
the BMC SPI controller where I was looking. May be the datasheet
was updated now ?
> Do you want to add the magic behavior to your model?
Yes. The Aspeed SPI driver needs them. I think the model can be better.
I will send a v2.
Thanks,
C.
>
>>
>> Cc: Chin-Ting Kuo <chin-ting_...@aspeedtech.com>
>> Signed-off-by: Cédric Le Goater <c...@kaod.org>
>> ---
>> hw/ssi/aspeed_smc.c | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
>> index e3d5e26058c0..c1557ef5d848 100644
>> --- a/hw/ssi/aspeed_smc.c
>> +++ b/hw/ssi/aspeed_smc.c
>> @@ -127,6 +127,8 @@
>>
>> /* DMA Control/Status Register */
>> #define R_DMA_CTRL (0x80 / 4)
>> +#define DMA_CTRL_REQUEST (1 << 31)
>> +#define DMA_CTRL_GRANT (1 << 30)
>> #define DMA_CTRL_DELAY_MASK 0xf
>> #define DMA_CTRL_DELAY_SHIFT 8
>> #define DMA_CTRL_FREQ_MASK 0xf
>> @@ -1237,6 +1239,11 @@ static void aspeed_smc_dma_done(AspeedSMCState *s)
>>
>> static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl)
>> {
>> + if (dma_ctrl & DMA_CTRL_REQUEST) {
>> + s->regs[R_DMA_CTRL] = dma_ctrl | DMA_CTRL_GRANT;
>> + return;
>> + }
>> +
>> if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
>> s->regs[R_DMA_CTRL] = dma_ctrl;
>>
>> --
>> 2.26.2
>>
