Instead of a collection of #ifdefs on arch_init.c, define QEMU_ARCH inside each cpu.h file.
Signed-off-by: Eduardo Habkost <ehabk...@redhat.com> --- Cc: Richard Henderson <richard.hender...@linaro.org> Cc: Peter Maydell <peter.mayd...@linaro.org> Cc: Michael Rolnik <mrol...@gmail.com> Cc: Sarah Harris <s.e.har...@kent.ac.uk> Cc: "Edgar E. Iglesias" <edgar.igles...@gmail.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Eduardo Habkost <ehabk...@redhat.com> Cc: Michael Walle <mich...@walle.cc> Cc: Laurent Vivier <laur...@vivier.eu> Cc: "Philippe Mathieu-Daudé" <f4...@amsat.org> Cc: Aurelien Jarno <aurel...@aurel32.net> Cc: Jiaxun Yang <jiaxun.y...@flygoat.com> Cc: Aleksandar Rikalo <aleksandar.rik...@syrmia.com> Cc: Anthony Green <gr...@moxielogic.com> Cc: Chris Wulff <crwu...@gmail.com> Cc: Marek Vasut <ma...@denx.de> Cc: Stafford Horne <sho...@gmail.com> Cc: David Gibson <da...@gibson.dropbear.id.au> Cc: Palmer Dabbelt <pal...@dabbelt.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Yoshinori Sato <ys...@users.sourceforge.jp> Cc: David Hildenbrand <da...@redhat.com> Cc: Cornelia Huck <coh...@redhat.com> Cc: Thomas Huth <th...@redhat.com> Cc: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Cc: Artyom Tarasenko <atar4q...@gmail.com> Cc: Guan Xuetao <g...@mprc.pku.edu.cn> Cc: Max Filippov <jcmvb...@gmail.com> Cc: qemu-devel@nongnu.org Cc: qemu-...@nongnu.org Cc: qemu-...@nongnu.org Cc: qemu-ri...@nongnu.org Cc: qemu-s3...@nongnu.org --- target/alpha/cpu.h | 1 + target/arm/cpu.h | 1 + target/avr/cpu.h | 1 + target/cris/cpu.h | 1 + target/hppa/cpu.h | 1 + target/i386/cpu.h | 1 + target/lm32/cpu.h | 1 + target/m68k/cpu.h | 1 + target/microblaze/cpu.h | 1 + target/mips/cpu.h | 1 + target/moxie/cpu.h | 1 + target/nios2/cpu.h | 1 + target/openrisc/cpu.h | 1 + target/ppc/cpu.h | 1 + target/riscv/cpu.h | 1 + target/rx/cpu.h | 1 + target/s390x/cpu.h | 1 + target/sh4/cpu.h | 1 + target/sparc/cpu.h | 1 + target/tricore/cpu.h | 1 + target/unicore32/cpu.h | 1 + target/xtensa/cpu.h | 1 + softmmu/arch_init.c | 46 ----------------------------------------- 23 files changed, 22 insertions(+), 46 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 82df108967..313a4e456e 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -438,6 +438,7 @@ void alpha_translate_init(void); #define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU #define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU +#define QEMU_ARCH QEMU_ARCH_ALPHA void alpha_cpu_list(void); /* you can call this signal handler from your SIGBUS and SIGSEGV diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e5514c8286..3f469a6485 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2822,6 +2822,7 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU +#define QEMU_ARCH QEMU_ARCH_ARM #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d148e8c75a..98f5df0ad7 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -31,6 +31,7 @@ #define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU #define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_AVR_CPU +#define QEMU_ARCH QEMU_ARCH_AVR #define TCG_GUEST_DEFAULT_MO 0 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d3b6492909..2482915699 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -249,6 +249,7 @@ enum { #define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU +#define QEMU_ARCH QEMU_ARCH_CRIS #define cpu_signal_handler cpu_cris_signal_handler diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 61178fa6a2..74d813289b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -242,6 +242,7 @@ static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) void hppa_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU +#define QEMU_ARCH QEMU_ARCH_HPPA static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, target_ureg off) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 88e8586f8f..03202f610c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1971,6 +1971,7 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_X86_CPU +#define QEMU_ARCH QEMU_ARCH_I386 #ifdef TARGET_X86_64 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index ea7c01ca8b..169c0ff19d 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -238,6 +238,7 @@ bool lm32_cpu_do_semihosting(CPUState *cs); #define LM32_CPU_TYPE_SUFFIX "-" TYPE_LM32_CPU #define LM32_CPU_TYPE_NAME(model) model LM32_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_LM32_CPU +#define QEMU_ARCH QEMU_ARCH_LM32 #define cpu_list lm32_cpu_list #define cpu_signal_handler cpu_lm32_signal_handler diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 521ac67cdd..87b5324b2c 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -514,6 +514,7 @@ enum { #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_M68K_CPU +#define QEMU_ARCH QEMU_ARCH_M68K #define cpu_signal_handler cpu_m68k_signal_handler #define cpu_list m68k_cpu_list diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c1c264199f..cbe60fbf58 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -378,6 +378,7 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo, void *puc); #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU +#define QEMU_ARCH QEMU_ARCH_MICROBLAZE #define cpu_signal_handler cpu_mb_signal_handler diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 23f8c6f96c..8a6707aa81 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1285,6 +1285,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU +#define QEMU_ARCH QEMU_ARCH_MIPS bool cpu_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const char *cpu_type, uint64_t isa); diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index bd6ab66084..f638509381 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -95,6 +95,7 @@ int cpu_moxie_signal_handler(int host_signum, void *pinfo, #define MOXIE_CPU_TYPE_SUFFIX "-" TYPE_MOXIE_CPU #define MOXIE_CPU_TYPE_NAME(model) model MOXIE_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_MOXIE_CPU +#define QEMU_ARCH QEMU_ARCH_MOXIE #define cpu_signal_handler cpu_moxie_signal_handler diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 86bbe1d867..b8fabdfb60 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -207,6 +207,7 @@ void nios2_check_interrupts(CPUNios2State *env); void do_nios2_semihosting(CPUNios2State *env); #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU +#define QEMU_ARCH QEMU_ARCH_NIOS2 #define cpu_gen_code cpu_nios2_gen_code #define cpu_signal_handler cpu_nios2_signal_handler diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index bd42faf144..68ff1d06c9 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -348,6 +348,7 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU +#define QEMU_ARCH QEMU_ARCH_OPENRISC typedef CPUOpenRISCState CPUArchState; typedef OpenRISCCPU ArchCPU; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2609e4082e..fd870c4cf4 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1334,6 +1334,7 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU +#define QEMU_ARCH QEMU_ARCH_PPC #define cpu_signal_handler cpu_ppc_signal_handler #define cpu_list ppc_cpu_list diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0a326c843..3f566b1c7f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -33,6 +33,7 @@ #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU +#define QEMU_ARCH QEMU_ARCH_RISCV #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 0b4b998c7b..05c195962a 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -122,6 +122,7 @@ typedef RXCPU ArchCPU; #define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU #define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_RX_CPU +#define QEMU_ARCH QEMU_ARCH_RX const char *rx_crname(uint8_t cr); void rx_cpu_do_interrupt(CPUState *cpu); diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 60d434d5ed..d528d18b6d 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -797,6 +797,7 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_S390_CPU +#define QEMU_ARCH QEMU_ARCH_S390X /* you can call this signal handler from your SIGBUS and SIGSEGV signal handlers to inform the virtual CPU of exceptions. non zero diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 714e3b5641..f0314774f8 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -249,6 +249,7 @@ void cpu_load_tlb(CPUSH4State * env); #define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU +#define QEMU_ARCH QEMU_ARCH_SH4 #define cpu_signal_handler cpu_sh4_signal_handler #define cpu_list sh4_cpu_list diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index b9369398f2..9d80f8b500 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -662,6 +662,7 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU +#define QEMU_ARCH QEMU_ARCH_SPARC #define cpu_signal_handler cpu_sparc_signal_handler #define cpu_list sparc_cpu_list diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index b82349d1b1..28c86f77b0 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -402,6 +402,7 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc, #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU +#define QEMU_ARCH QEMU_ARCH_TRICORE /* helpers.c */ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 7a32e086ed..6c0d88aa9b 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -147,6 +147,7 @@ typedef UniCore32CPU ArchCPU; #define UNICORE32_CPU_TYPE_SUFFIX "-" TYPE_UNICORE32_CPU #define UNICORE32_CPU_TYPE_NAME(model) model UNICORE32_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_UNICORE32_CPU +#define QEMU_ARCH QEMU_ARCH_UNICORE32 static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 3bd4f691c1..c7a503b01d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -589,6 +589,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU +#define QEMU_ARCH QEMU_ARCH_XTENSA #ifdef TARGET_WORDS_BIGENDIAN #define XTENSA_DEFAULT_CPU_MODEL "fsf" diff --git a/softmmu/arch_init.c b/softmmu/arch_init.c index 7fd5c09b2b..7ef32a98b9 100644 --- a/softmmu/arch_init.c +++ b/softmmu/arch_init.c @@ -48,52 +48,6 @@ int graphic_depth = 32; #endif -#if defined(TARGET_ALPHA) -#define QEMU_ARCH QEMU_ARCH_ALPHA -#elif defined(TARGET_ARM) -#define QEMU_ARCH QEMU_ARCH_ARM -#elif defined(TARGET_CRIS) -#define QEMU_ARCH QEMU_ARCH_CRIS -#elif defined(TARGET_HPPA) -#define QEMU_ARCH QEMU_ARCH_HPPA -#elif defined(TARGET_I386) -#define QEMU_ARCH QEMU_ARCH_I386 -#elif defined(TARGET_LM32) -#define QEMU_ARCH QEMU_ARCH_LM32 -#elif defined(TARGET_M68K) -#define QEMU_ARCH QEMU_ARCH_M68K -#elif defined(TARGET_MICROBLAZE) -#define QEMU_ARCH QEMU_ARCH_MICROBLAZE -#elif defined(TARGET_MIPS) -#define QEMU_ARCH QEMU_ARCH_MIPS -#elif defined(TARGET_MOXIE) -#define QEMU_ARCH QEMU_ARCH_MOXIE -#elif defined(TARGET_NIOS2) -#define QEMU_ARCH QEMU_ARCH_NIOS2 -#elif defined(TARGET_OPENRISC) -#define QEMU_ARCH QEMU_ARCH_OPENRISC -#elif defined(TARGET_PPC) -#define QEMU_ARCH QEMU_ARCH_PPC -#elif defined(TARGET_RISCV) -#define QEMU_ARCH QEMU_ARCH_RISCV -#elif defined(TARGET_RX) -#define QEMU_ARCH QEMU_ARCH_RX -#elif defined(TARGET_S390X) -#define QEMU_ARCH QEMU_ARCH_S390X -#elif defined(TARGET_SH4) -#define QEMU_ARCH QEMU_ARCH_SH4 -#elif defined(TARGET_SPARC) -#define QEMU_ARCH QEMU_ARCH_SPARC -#elif defined(TARGET_TRICORE) -#define QEMU_ARCH QEMU_ARCH_TRICORE -#elif defined(TARGET_UNICORE32) -#define QEMU_ARCH QEMU_ARCH_UNICORE32 -#elif defined(TARGET_XTENSA) -#define QEMU_ARCH QEMU_ARCH_XTENSA -#elif defined(TARGET_AVR) -#define QEMU_ARCH QEMU_ARCH_AVR -#endif - const uint32_t arch_type = QEMU_ARCH; int kvm_available(void) -- 2.28.0