Claudio Fontana <cfont...@suse.de> writes:
> From: Eduardo Habkost <ehabk...@redhat.com>
>
> Signed-off-by: Eduardo Habkost <ehabk...@redhat.com>
> [claudio: wrapped in CONFIG_TCG]
> Signed-off-by: Claudio Fontana <cfont...@suse.de>
> Reviewed-by: Philippe Mathieu-Daudé <phi...@redhat.com>
> ---
> accel/tcg/cputlb.c | 6 +++---
> accel/tcg/user-exec.c | 6 +++---
> include/hw/core/cpu.h | 9 ---------
> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++
> target/alpha/cpu.c | 2 +-
> target/arm/cpu.c | 2 +-
> target/avr/cpu.c | 2 +-
> target/cris/cpu.c | 2 +-
> target/hppa/cpu.c | 2 +-
> target/i386/tcg-cpu.c | 2 +-
> target/lm32/cpu.c | 2 +-
> target/m68k/cpu.c | 2 +-
> target/microblaze/cpu.c | 2 +-
> target/mips/cpu.c | 2 +-
> target/moxie/cpu.c | 2 +-
> target/nios2/cpu.c | 2 +-
> target/openrisc/cpu.c | 2 +-
> target/ppc/translate_init.c.inc | 2 +-
> target/riscv/cpu.c | 2 +-
> target/rx/cpu.c | 2 +-
> target/s390x/cpu.c | 2 +-
> target/sh4/cpu.c | 2 +-
> target/sparc/cpu.c | 2 +-
> target/tilegx/cpu.c | 2 +-
> target/tricore/cpu.c | 2 +-
> target/unicore32/cpu.c | 2 +-
> target/xtensa/cpu.c | 2 +-
> 27 files changed, 41 insertions(+), 38 deletions(-)
>
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index 42ab79c1a5..2dc71b5528 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -1286,7 +1286,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr,
> int size,
> * This is not a probe, so only valid return is success; failure
> * should result in exception + longjmp to the cpu loop.
> */
> - ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr);
> + ok = cc->tcg_ops.tlb_fill(cpu, addr, size, access_type, mmu_idx, false,
> retaddr);
> assert(ok);
> }
>
> @@ -1557,8 +1557,8 @@ static int probe_access_internal(CPUArchState *env,
> target_ulong addr,
> CPUState *cs = env_cpu(env);
> CPUClass *cc = CPU_GET_CLASS(cs);
>
> - if (!cc->tlb_fill(cs, addr, fault_size, access_type,
> - mmu_idx, nonfault, retaddr)) {
> + if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_type,
> + mmu_idx, nonfault, retaddr)) {
> /* Non-faulting page table read failed. */
> *phost = NULL;
> return TLB_INVALID_MASK;
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 4ebe25461a..7f53992251 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -186,7 +186,7 @@ static inline int handle_cpu_signal(uintptr_t pc,
> siginfo_t *info,
> clear_helper_retaddr();
>
> cc = CPU_GET_CLASS(cpu);
> - cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
> + cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false,
> pc);
> g_assert_not_reached();
> }
>
> @@ -216,8 +216,8 @@ static int probe_access_internal(CPUArchState *env,
> target_ulong addr,
> } else {
> CPUState *cpu = env_cpu(env);
> CPUClass *cc = CPU_GET_CLASS(cpu);
> - cc->tlb_fill(cpu, addr, fault_size, access_type,
> - MMU_USER_IDX, false, ra);
> + cc->tcg_ops.tlb_fill(cpu, addr, fault_size, access_type,
> + MMU_USER_IDX, false, ra);
> g_assert_not_reached();
> }
> }
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 52142e9094..c82ef261c6 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -110,12 +110,6 @@ struct TranslationBlock;
> * If the target behaviour here is anything other than "set
> * the PC register to the value passed in" then the target must
> * also implement the synchronize_from_tb hook.
> - * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
> - * address fault. For system mode, if the access is valid, call
> - * tlb_set_page and return true; if the access is invalid, and
> - * probe is true, return false; otherwise raise an exception and
> - * do not return. For user-only mode, always raise an exception
> - * and do not return.
> * @get_phys_page_debug: Callback for obtaining a physical address.
> * @get_phys_page_attrs_debug: Callback for obtaining a physical address and
> the
> * associated memory transaction attributes to use for the access.
> @@ -183,9 +177,6 @@ struct CPUClass {
> void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
> Error **errp);
> void (*set_pc)(CPUState *cpu, vaddr value);
> - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
> - MMUAccessType access_type, int mmu_idx,
> - bool probe, uintptr_t retaddr);
> hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
> hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
> MemTxAttrs *attrs);
> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
> index e12f32919b..2ea94acca0 100644
> --- a/include/hw/core/tcg-cpu-ops.h
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -37,6 +37,18 @@ typedef struct TcgCpuOperations {
> void (*cpu_exec_exit)(CPUState *cpu);
> /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec
> */
> bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
> + /**
> + * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
> + *
> + * For system mode, if the access is valid, call tlb_set_page
> + * and return true; if the access is invalid, and probe is
> + * true, return false; otherwise raise an exception and do
> + * not return. For user-only mode, always raise an exception
> + * and do not return.
> + */
> + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
> + MMUAccessType access_type, int mmu_idx,
> + bool probe, uintptr_t retaddr);
As per previous patch, here is a chance to clean-up the comment.
Otherwise:
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
--
Alex Bennée
