From: Frank Chang <frank.ch...@sifive.com> This patchset implements RISC-V B-extension draft version Zbb, Zbs and Zba subset instructions. Some Zbp instructions are also implemented as they have similar behavior with their Zbb-, Zbs- and Zba-family instructions or for Zbb pseudo instructions (e.g. rev8, orc.b).
Specification: https://github.com/riscv/riscv-bitmanip Summary of current proposals for Zb{abcs}: https://lists.riscv.org/g/tech-bitmanip/topic/summary_of_current_proposals/77924315 The port is available here: https://github.com/sifive/qemu/tree/rvb-upstream-v2 To test rvb implementation, specify cpu argument with 'x-b=true' to enable B-extension support. Changelog: v2: * Add gen_shifti(), gen_shiftw(), gen_shiftiw() helper functions. * Remove addwu, subwu and addiwu instructions as they are not longer exist in latest draft. * Optimize implementation with cleaner tcg ops. Frank Chang (3): target/riscv: rvb: count bits set target/riscv: rvb: generalized reverse target/riscv: rvb: generalized or-combine Kito Cheng (12): target/riscv: reformat @sh format encoding for B-extension target/riscv: rvb: count leading/trailing zeros target/riscv: rvb: logic-with-negate target/riscv: rvb: pack two words into one register target/riscv: rvb: min/max instructions target/riscv: rvb: sign-extend instructions target/riscv: rvb: single-bit instructions target/riscv: rvb: shift ones target/riscv: rvb: rotate (left/right) target/riscv: rvb: address calculation target/riscv: rvb: add/sub with postfix zero-extend target/riscv: rvb: support and turn on B-extension from command line target/riscv/bitmanip_helper.c | 103 ++++++ target/riscv/cpu.c | 4 + target/riscv/cpu.h | 2 + target/riscv/helper.h | 9 + target/riscv/insn32-64.decode | 33 ++ target/riscv/insn32.decode | 54 ++- target/riscv/insn_trans/trans_rvb.c.inc | 466 ++++++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 337 +++++++++++++++++ 9 files changed, 1003 insertions(+), 6 deletions(-) create mode 100644 target/riscv/bitmanip_helper.c create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc -- 2.17.1
