On 08/30/2011 05:07 AM, Daniel Verkamp wrote:
On Sun, Aug 28, 2011 at 11:48 AM, Alexander Graf<ag...@suse.de> wrote:
On 27.08.2011, at 04:12, Daniel Verkamp wrote:
Implement an I/O space index-data register pair as defined by the AHCI
spec, including the corresponding SATA PCI capability and BAR.
This allows real-mode code to access the AHCI registers; real-mode
code cannot address the memory-mapped register space because it is
beyond the first megabyte.
Very nice patch! I'll check and compare with a real ICH-9 when I get
back to .de, but I'd assume you also did that already ;). Once I checked
that the IO region is set up similarly, I'll give you my ack.
Please do double check against real hardware if you get the chance - I
don't have a real ICH-9 handy to test against. This is all written
based on my reading of the spec and testing with an internal DOS
developer tool from work.
I am mainly curious how the real thing handles writes to the index
register that aren't divisible by 4 or are beyond the end of the
register set (and how big that really is on ICH-9). Judging by the
bits marked "RO" in the spec, I would guess writing 0x13 to the index
and then reading it back should give 0x10, but I haven't tested it on
real hw.
Phew. So I finally got at least an ICH-9 system booting. This is what
lspci -vvv tells me:
00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6
port SATA AHCI Controller (rev 02) (prog-if 01 [AHCI 1.0])
Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port
SATA AHCI Controller
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin B routed to IRQ 26
Region 0: I/O ports at d000 [size=8]
Region 1: I/O ports at cc00 [size=4]
Region 2: I/O ports at c880 [size=8]
Region 3: I/O ports at c800 [size=4]
Region 4: I/O ports at c480 [size=32]
Region 5: Memory at ffaf9000 (32-bit, non-prefetchable) [size=2K]
Capabilities: [80] MSI: Enable+ Count=1/16 Maskable- 64bit-
Address: fee0f00c Data: 4169
Capabilities: [70] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot+,D3cold-)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [a8] SATA HBA v1.0 BAR4 Offset=00000004
Capabilities: [b0] Vendor Specific Information: Len=06 <?>
Kernel driver in use: ahci
So BAR4 is where the IDP info should be. Offset is 4 into that IO space
and the space is 32 bytes long. Do you have the ICH-9 implementation
spec? I can try to dig something up if you don't have it around.
Please send me a small test program I can run on the machine to find out
what happens for unaligned I/O accesses. That would be very helpful!
Thanks,
Alex
