On Tue, 29 Dec 2020, Mark Cave-Ayland wrote:
On 28/12/2020 20:50, BALATON Zoltan via wrote:
I think leaving the legacy ports enabled is a bad idea for at least two
reasons: 1) It may clash with other io ports on other machines, e.g. I'm
not sure on PPC where firmware or OS does not expect to see legacy ISA
ports won't map some io BAR of a PCI card there. 2) If this is left enabled
there would be two ports poking the same registers so if that does not
cause a problem by itself, writing to one accidentally (like when something
is mapped over it) could cause corruption of IDE state so I think it's much
better to protect this than later trying to debug such problems.
Legacy ioports originate in the x86 world, however all the PCI bus
enumeration code I've seen reserves the lower part of the IO address space to
prevent such problems with e.g. a BIOS starting up in legacy mode.
I don't remember the details and won't test it again but PPC has neither
BIOS nor legacy io ports (or io ports for that matter, all that is memory
mapped). If you want go back to the email thread in March where I've
described in detail how I ended up with these and what are the assumptions
of guests I've tested and tried to satisfy with this.
Stop trying to compare it with hardware and look at it in a way that we
want to make a device model that works with the guests we want to run. In
that frame this works and probably the simplest way. Unless you fully want
to implement all the quirks of the chip and take up all the clean up in
QEMU needed for that (possibly risking breaking a lot of other boards
along the way) this won't match hardware 100%.
Regards,
BALATON Zoltan