On Tue, Jan 12, 2021 at 1:44 AM <frank.ch...@sifive.com> wrote: > > From: Frank Chang <frank.ch...@sifive.com> > > Signed-off-by: Frank Chang <frank.ch...@sifive.com> > Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/vector_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index a156573d281..bc3f212ceac 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -98,7 +98,7 @@ static inline uint32_t vext_lmul(uint32_t desc) > > static uint32_t vext_wd(uint32_t desc) > { > - return (simd_data(desc) >> 11) & 0x1; > + return FIELD_EX32(simd_data(desc), VDATA, WD); > } > > /* > -- > 2.17.1 > >