On Tue, Jan 12, 2021 at 1:42 AM <frank.ch...@sifive.com> wrote:
>
> From: Frank Chang <frank.ch...@sifive.com>
>
> Implementations may have a writable misa.v field. Analogous to the way
> in which the floating-point unit is handled, the mstatus.vs field may
> exist even if misa.v is clear.
>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index a70a78386da..c8b1e4954ec 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -579,7 +579,7 @@ static int write_misa(CPURISCVState *env, int csrno,
> target_ulong val)
> val &= env->misa_mask;
>
> /* Mask extensions that are not supported by QEMU */
> - val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> + val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
>
> /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
> if ((val & RVD) && !(val & RVF)) {
> --
> 2.17.1
>
>
