On Wed, 10 Feb 2021 at 18:05, Daniel Müller via <qemu-devel@nongnu.org> wrote: > > When working with performance monitoring counters, we look at > MDCR_EL2.HPMN as part of the check whether a counter is enabled. This > check fails, because MDCR_EL2.HPMN is reset to 0, meaning that no > counters are "enabled" for < EL2. > That's in violation of the Arm specification, which states that > > > On a Warm reset, this field [MDCR_EL2.HPMN] resets to the value in > > PMCR_EL0.N > > That's also what a comment in the code acknowledges, but the necessary > adjustment seems to have been forgotten when support for more counters > was added. > This change fixes the issue by setting the reset value to PMCR.N, which > is four. > --- > target/arm/helper.c | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) >
Applied to target-arm.next, thanks. -- PMM
