On Tue, 16 Feb 2021 at 22:45, Rebecca Cran <rebe...@nuviainc.com> wrote:
>
> Enable FEAT_SSBS for the "max" 32-bit CPU.
>
> Signed-off-by: Rebecca Cran <rebe...@nuviainc.com>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/cpu.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 5cf6c056c50f..88a6b183d325 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2206,6 +2206,10 @@ static void arm_max_initfn(Object *obj)
> t = cpu->isar.id_pfr0;
> t = FIELD_DP32(t, ID_PFR0, DIT, 1);
> cpu->isar.id_pfr0 = t;
> +
> + t = cpu->isar.id_pfr2;
> + t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
> + cpu->isar.id_mfr2 = t;
Er, this doesn't compile:
../../target/arm/cpu.c:2223:19: error: no member named 'id_mfr2' in
'struct ARMISARegisters'
cpu->isar.id_mfr2 = t;
~~~~~~~~~ ^
The typo is obvious, so I'm just going to fix it up in the
target-arm queue, but this does suggest that your testing process
before sending out patches could be improved ;-)
thanks
-- PMM
