On Sat, 6 Mar 2021 at 16:54, Keith Packard <kei...@keithp.com> wrote: > > Peter Maydell <peter.mayd...@linaro.org> writes: > > Part of why I asked is that the current RISCV implementation > > is just looking at sizeof(target_ulong); but the qemu-system-riscv64 > > executable AIUI now supports emulating both "this is a 64 bit > > guest CPU" and "this is a 32 bit host CPU", and so looking at > > a QEMU-compile-time value like "sizeof(target_ulong)" will > > produce the wrong answer for 32-bit CPUs emulated in > > the qemu-system-riscv64 binary. My guess is maybe > > it should be looking at the result of riscv_cpu_is_32bit() instead. > > Wow. I read through the code and couldn't find anything that looked like > it supported that, sounds like I must have missed something?
I thought Alistair had done that work (which brings riscv into line with the other 32/64 bit QEMU targets, which all support the 32-bit CPU types in the 64-bit-capable executable). But maybe it hasn't landed in master yet? thanks -- PMM
