On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K <vi...@behindbytes.com> wrote: > > Changes in v3: > - Drop SHAKTI_C_DEBUG register > > Changes in v2: > - Moved CPU addition to a separate patch(P1) > - Use riscv_setup_rom_resetvec API to setup reset vector > - Dropped unused DPRINTF and unwanted break statements > - Fixed uart_can_receive logic > - Reused sifive_u_cpu_init routine for shakti > - Error out when an unsupported CPU is specified > - Addressed formatting changes pointed out in review
Thanks, I have reviewed these patches and applied them. Can you add details to the docs on how to build images and run this machine? This is an example for a different board: https://gitlab.com/qemu-project/qemu/-/blob/master/docs/system/riscv/microchip-icicle-kit.rst That way others can use this machine and I can generate tests for it. Alistair > > Vijai Kumar K (4): > target/riscv: Add Shakti C class CPU > riscv: Add initial support for Shakti C machine > hw/char: Add Shakti UART emulation > hw/riscv: Connect Shakti UART to Shakti platform > > MAINTAINERS | 9 + > default-configs/devices/riscv64-softmmu.mak | 1 + > hw/char/meson.build | 1 + > hw/char/shakti_uart.c | 185 ++++++++++++++++++++ > hw/char/trace-events | 4 + > hw/riscv/Kconfig | 10 ++ > hw/riscv/meson.build | 1 + > hw/riscv/shakti_c.c | 178 +++++++++++++++++++ > include/hw/char/shakti_uart.h | 74 ++++++++ > include/hw/riscv/shakti_c.h | 75 ++++++++ > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > 12 files changed, 540 insertions(+) > create mode 100644 hw/char/shakti_uart.c > create mode 100644 hw/riscv/shakti_c.c > create mode 100644 include/hw/char/shakti_uart.h > create mode 100644 include/hw/riscv/shakti_c.h > > -- > 2.25.1 > >
