On Mon, May 17, 2021 at 04:40:32PM -0500, Paul A. Clarke wrote:
> `lxvdsx` is byte-swapping the data it loads, which it should not
> do. Fix it.
>
> Fixes #212.
>
> Fixes: bcb0b7b1a1c05707304f80ca6f523d557816f85c
> Signed-off-by: Paul A. Clarke <p...@us.ibm.com
nit, missing '>' ...^
I'm having a hard time convincing myself this is correct in all cases.
Have you tested it with all combinations of BE/LE host and BE/LE guest
code?
The description in the ISA is pretty inscrutable, since it's in terms
of the confusing numbering if different element types in BE vs LE
mode.
It looks to me like before bcb0b7b1a1c0 this originally resolved to
MO_Q modified by ctx->default_tcg_memop_mask, which appears to depend
on the current guest endian mode. That's pretty hard to trace through
the various layers of macros, but for reference, before bcb0b7b1a1c0
this used gen_qemu_ld64_i64(), which appears to be constructed by the
line GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) in translate.c.
Richard or Giuseppe, care to weigh in?
> ---
> target/ppc/translate/vsx-impl.c.inc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/ppc/translate/vsx-impl.c.inc
> b/target/ppc/translate/vsx-impl.c.inc
> index b817d31260bb..46f97c029ca8 100644
> --- a/target/ppc/translate/vsx-impl.c.inc
> +++ b/target/ppc/translate/vsx-impl.c.inc
> @@ -162,7 +162,7 @@ static void gen_lxvdsx(DisasContext *ctx)
> gen_addr_reg_index(ctx, EA);
>
> data = tcg_temp_new_i64();
> - tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_TEQ);
> + tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_LEQ);
> tcg_gen_gvec_dup_i64(MO_Q, vsr_full_offset(xT(ctx->opcode)), 16, 16,
> data);
>
> tcg_temp_free(EA);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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