Hi Ruinland, On Thu, Jun 10, 2021 at 10:45 PM Ruinland Chuan-Tzu Tsai <ruinl...@andestech.com> wrote: > > From: Ruinaldn ChuanTzu Tsai <ruinl...@andestech.com> > > Adding the skeleton of Andes Technology AX25 CPU model for the future commits, > which will utilize custom/vendor CSR handling mechaism.
typo: mechanism > --- > target/riscv/cpu.c | 8 ++++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 9 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ddea8fbeeb..4ae21cbf9b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -159,6 +159,13 @@ static void rv64_base_cpu_init(Object *obj) > set_misa(env, RV64); > } > > +static void ax25_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > + > static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -705,6 +712,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_AX25, ax25_cpu_init), What about the 32-bit variant of A25, and the SMP variant of A25MP/AX25MP? Also how about the latest A45 (RV32) and AX45 (RV64)? How should we name these? I think we may need to name this using the SMP variant name, no? > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), > #endif Regards, Bin