Re: [PATCH v2 04/21] target/riscv: Introduce DisasExtend and new helpers

[Richard Henderson]

On 8/18/21 12:58 AM, Bin Meng wrote:

+static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
+{
+    if (reg_num != 0) {
+        if (ctx->w) {
+            tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);

What about zero extension?

All of the RV64 word instructions sign-extend the result.

  void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
  {
-    DisasContext ctx;
+    DisasContext ctx = { };

Why is this change? I believe we should explicitly initialize the ctx
in riscv_tr_init_disas_context()

I considered it easier to zero-init the whole thing here.

r~