Replace use of tcg_const_*, which makes a copy into a temp which must
be freed, with direct use of the constant. Reorg handling of $zero,
with different accessors for source and destination. Reorg handling
of csrs, passing the actual write_mask instead of a regno. Use more
helpers for RVH expansion.
Patches lacking review:
13-target-riscv-Use-extracts-for-sraiw-and-srliw.patch (new)
16-target-riscv-Fix-rmw_sip-rmw_vsip-rmw_hsip-vs-wri.patch (new)
17-target-riscv-Fix-hgeie-hgeip.patch (new)
20-target-riscv-Use-gen_shift_imm_fn-for-slli_uw.patch
24-target-riscv-Use-get-dest-_gpr-for-RVV.patch
Changes for v5:
* Use extract for sraiw, srliw.
* Fix some broken csr helpers.
Changes for v4:
* Add a test for division, primarily checking the edge cases.
* Dropped the greviw patch, since grev has been dropped from Zbb 1.0.0.
Changes for v3:
* Fix an introduced remainder bug (bin meng),
and remove one extra movcond from rem/remu.
* Do not zero DisasContext on allocation (bin meng).
Changes for v2:
* Retain the requirement to call gen_set_gpr.
* Add DisasExtend as an argument to get_gpr, and ctx->w as a member
of DisasContext. This should help in implementing UXL, where we
should be able to set ctx->w for all insns, but there is certainly
more required for that.
r~
Richard Henderson (24):
target/riscv: Use tcg_constant_*
tests/tcg/riscv64: Add test for division
target/riscv: Clean up division helpers
target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
target/riscv: Introduce DisasExtend and new helpers
target/riscv: Add DisasExtend to gen_arith*
target/riscv: Remove gen_arith_div*
target/riscv: Use gen_arith for mulh and mulhu
target/riscv: Move gen_* helpers for RVM
target/riscv: Move gen_* helpers for RVB
target/riscv: Add DisasExtend to gen_unary
target/riscv: Use DisasExtend in shift operations
target/riscv: Use extracts for sraiw and srliw
target/riscv: Use get_gpr in branches
target/riscv: Use {get,dest}_gpr for integer load/store
target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation
target/riscv: Fix hgeie, hgeip
target/riscv: Reorg csr instructions
target/riscv: Use {get,dest}_gpr for RVA
target/riscv: Use gen_shift_imm_fn for slli_uw
target/riscv: Use {get,dest}_gpr for RVF
target/riscv: Use {get,dest}_gpr for RVD
target/riscv: Tidy trans_rvh.c.inc
target/riscv: Use {get,dest}_gpr for RVV
target/riscv/helper.h | 6 +-
target/riscv/insn32.decode | 1 +
target/riscv/csr.c | 49 +-
target/riscv/op_helper.c | 18 +-
target/riscv/translate.c | 701 ++++++------------------
tests/tcg/riscv64/test-div.c | 58 ++
target/riscv/insn_trans/trans_rva.c.inc | 51 +-
target/riscv/insn_trans/trans_rvb.c.inc | 366 ++++++++++---
target/riscv/insn_trans/trans_rvd.c.inc | 127 +++--
target/riscv/insn_trans/trans_rvf.c.inc | 149 +++--
target/riscv/insn_trans/trans_rvh.c.inc | 266 ++-------
target/riscv/insn_trans/trans_rvi.c.inc | 370 +++++++------
target/riscv/insn_trans/trans_rvm.c.inc | 191 +++++--
target/riscv/insn_trans/trans_rvv.c.inc | 151 ++---
tests/tcg/riscv64/Makefile.target | 5 +
15 files changed, 1154 insertions(+), 1355 deletions(-)
create mode 100644 tests/tcg/riscv64/test-div.c
create mode 100644 tests/tcg/riscv64/Makefile.target
--
2.25.1
