On Thu, Aug 26, 2021 at 3:05 AM Philipp Tomsich
<philipp.toms...@vrull.eu> wrote:
>
> The following instructions are part of Zbs:
> - b{set,clr,ext,inv}
> - b{set,clr,ext,inv}i
>
> Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - The changes to the Zbs instructions (i.e. the REQUIRE_ZBS macro) and
> its use for qualifying the Zba instructions) are moved into a
> separate commit.
>
> target/riscv/insn32.decode | 17 +++++++++--------
> target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++++++++---------
> 2 files changed, 24 insertions(+), 17 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 7e38477553..1166e7f648 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -688,19 +688,11 @@ min 0000101 .......... 100 ..... 0110011 @r
> minu 0000101 .......... 101 ..... 0110011 @r
> max 0000101 .......... 110 ..... 0110011 @r
> maxu 0000101 .......... 111 ..... 0110011 @r
> -bset 0010100 .......... 001 ..... 0110011 @r
> -bclr 0100100 .......... 001 ..... 0110011 @r
> -binv 0110100 .......... 001 ..... 0110011 @r
> -bext 0100100 .......... 101 ..... 0110011 @r
> ror 0110000 .......... 101 ..... 0110011 @r
> rol 0110000 .......... 001 ..... 0110011 @r
> grev 0110100 .......... 101 ..... 0110011 @r
> gorc 0010100 .......... 101 ..... 0110011 @r
>
> -bseti 00101. ........... 001 ..... 0010011 @sh
> -bclri 01001. ........... 001 ..... 0010011 @sh
> -binvi 01101. ........... 001 ..... 0010011 @sh
> -bexti 01001. ........... 101 ..... 0010011 @sh
> rori 01100. ........... 101 ..... 0010011 @sh
> grevi 01101. ........... 101 ..... 0010011 @sh
> gorci 00101. ........... 101 ..... 0010011 @sh
> @@ -721,3 +713,12 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
> greviw 0110100 .......... 101 ..... 0011011 @sh5
> gorciw 0010100 .......... 101 ..... 0011011 @sh5
>
> +# *** RV32 Zbs Standard Extension ***
> +bclr 0100100 .......... 001 ..... 0110011 @r
> +bclri 01001. ........... 001 ..... 0010011 @sh
> +bext 0100100 .......... 101 ..... 0110011 @r
> +bexti 01001. ........... 101 ..... 0010011 @sh
> +binv 0110100 .......... 001 ..... 0110011 @r
> +binvi 01101. ........... 001 ..... 0010011 @sh
> +bset 0010100 .......... 001 ..... 0110011 @r
> +bseti 00101. ........... 001 ..... 0010011 @sh
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index ac706349f5..21d713df27 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -1,5 +1,5 @@
> /*
> - * RISC-V translation routines for the RVB draft and Zba Standard Extension.
> + * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
> *
> * Copyright (c) 2020 Kito Cheng, kito.ch...@sifive.com
> * Copyright (c) 2020 Frank Chang, frank.ch...@sifive.com
> @@ -24,6 +24,12 @@
> } \
> } while (0)
>
> +#define REQUIRE_ZBS(ctx) do { \
> + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
> + return false; \
> + } \
> +} while (0)
> +
> static bool trans_clz(DisasContext *ctx, arg_clz *a)
> {
> REQUIRE_EXT(ctx, RVB);
> @@ -116,49 +122,49 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h
> *a)
>
> static bool trans_bset(DisasContext *ctx, arg_bset *a)
> {
> - REQUIRE_EXT(ctx, RVB);
> + REQUIRE_ZBS(ctx);
> return gen_shift(ctx, a, gen_bset);
> }
>
> static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
> {
> - REQUIRE_EXT(ctx, RVB);
> + REQUIRE_ZBS(ctx);
> return gen_shifti(ctx, a, gen_bset);
> }
>
> static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
> {
> - REQUIRE_EXT(ctx, RVB);
> + REQUIRE_ZBS(ctx);
> return gen_shift(ctx, a, gen_bclr);
> }
>
> static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
> {
> - REQUIRE_EXT(ctx, RVB);
> + REQUIRE_ZBS(ctx);
> return gen_shifti(ctx, a, gen_bclr);
> }
>
> static bool trans_binv(DisasContext *ctx, arg_binv *a)
> {
> - REQUIRE_EXT(ctx, RVB);
> + REQUIRE_ZBS(ctx);
> return gen_shift(ctx, a, gen_binv);
> }
>
> static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
> {
> - REQUIRE_EXT(ctx, RVB);
> + REQUIRE_ZBS(ctx);
> return gen_shifti(ctx, a, gen_binv);
> }
>
> static bool trans_bext(DisasContext *ctx, arg_bext *a)
> {
> - REQUIRE_EXT(ctx, RVB);
> + REQUIRE_ZBS(ctx);
> return gen_shift(ctx, a, gen_bext);
> }
>
> static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
> {
> - REQUIRE_EXT(ctx, RVB);
> + REQUIRE_ZBS(ctx);
> return gen_shifti(ctx, a, gen_bext);
> }
>
> --
> 2.25.1
>
>
